[53dd6d61] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup arm_beagle |
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| 5 | * |
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| 6 | * @brief Clock driver configuration. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2014 Ben Gras <beng@shrike-systems.com>. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[d4edbdbc] | 14 | * http://www.rtems.org/license/LICENSE. |
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[53dd6d61] | 15 | */ |
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| 16 | |
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| 17 | #include <rtems.h> |
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[75acd9e] | 18 | #include <rtems/timecounter.h> |
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[53dd6d61] | 19 | #include <bsp.h> |
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| 20 | |
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| 21 | #include <libcpu/omap_timer.h> |
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| 22 | |
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[75acd9e] | 23 | static struct timecounter beagle_clock_tc; |
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[53dd6d61] | 24 | |
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| 25 | static omap_timer_registers_t regs_v1 = { |
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| 26 | .TIDR = OMAP3_TIMER_TIDR, |
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| 27 | .TIOCP_CFG = OMAP3_TIMER_TIOCP_CFG, |
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| 28 | .TISTAT = OMAP3_TIMER_TISTAT, |
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| 29 | .TISR = OMAP3_TIMER_TISR, |
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| 30 | .TIER = OMAP3_TIMER_TIER, |
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| 31 | .TWER = OMAP3_TIMER_TWER, |
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| 32 | .TCLR = OMAP3_TIMER_TCLR, |
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| 33 | .TCRR = OMAP3_TIMER_TCRR, |
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| 34 | .TLDR = OMAP3_TIMER_TLDR, |
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| 35 | .TTGR = OMAP3_TIMER_TTGR, |
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| 36 | .TWPS = OMAP3_TIMER_TWPS, |
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| 37 | .TMAR = OMAP3_TIMER_TMAR, |
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| 38 | .TCAR1 = OMAP3_TIMER_TCAR1, |
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| 39 | .TSICR = OMAP3_TIMER_TSICR, |
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| 40 | .TCAR2 = OMAP3_TIMER_TCAR2, |
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| 41 | .TPIR = OMAP3_TIMER_TPIR, |
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| 42 | .TNIR = OMAP3_TIMER_TNIR, |
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| 43 | .TCVR = OMAP3_TIMER_TCVR, |
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| 44 | .TOCR = OMAP3_TIMER_TOCR, |
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| 45 | .TOWR = OMAP3_TIMER_TOWR, |
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| 46 | }; |
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| 47 | |
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[1e587f7d] | 48 | #if IS_AM335X |
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[53dd6d61] | 49 | /* AM335X has a different ip block for the non 1ms timers */ |
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| 50 | static omap_timer_registers_t regs_v2 = { |
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| 51 | .TIDR = AM335X_TIMER_TIDR, |
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| 52 | .TIOCP_CFG = AM335X_TIMER_TIOCP_CFG, |
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| 53 | .TISTAT = AM335X_TIMER_IRQSTATUS_RAW, |
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| 54 | .TISR = AM335X_TIMER_IRQSTATUS, |
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| 55 | .TIER = AM335X_TIMER_IRQENABLE_SET, |
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| 56 | .TWER = AM335X_TIMER_IRQWAKEEN, |
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| 57 | .TCLR = AM335X_TIMER_TCLR, |
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| 58 | .TCRR = AM335X_TIMER_TCRR, |
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| 59 | .TLDR = AM335X_TIMER_TLDR, |
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| 60 | .TTGR = AM335X_TIMER_TTGR, |
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| 61 | .TWPS = AM335X_TIMER_TWPS, |
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| 62 | .TMAR = AM335X_TIMER_TMAR, |
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| 63 | .TCAR1 = AM335X_TIMER_TCAR1, |
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| 64 | .TSICR = AM335X_TIMER_TSICR, |
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| 65 | .TCAR2 = AM335X_TIMER_TCAR2, |
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| 66 | .TPIR = -1, /* UNDEF */ |
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| 67 | .TNIR = -1, /* UNDEF */ |
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| 68 | .TCVR = -1, /* UNDEF */ |
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| 69 | .TOCR = -1, /* UNDEF */ |
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| 70 | .TOWR = -1 /* UNDEF */ |
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| 71 | }; |
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[1e587f7d] | 72 | #endif |
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[53dd6d61] | 73 | |
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| 74 | /* which timers are in use? target-dependent. |
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| 75 | * initialize at compile time. |
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| 76 | */ |
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| 77 | |
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| 78 | #if IS_DM3730 |
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| 79 | |
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| 80 | static omap_timer_t dm37xx_timer = { |
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| 81 | .base = OMAP3_GPTIMER1_BASE, |
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| 82 | .irq_nr = OMAP3_GPT1_IRQ, |
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| 83 | .regs = ®s_v1 |
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| 84 | }; |
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| 85 | |
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| 86 | /* free running timer */ |
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| 87 | static omap_timer_t dm37xx_fr_timer = { |
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| 88 | .base = OMAP3_GPTIMER10_BASE, |
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| 89 | .irq_nr = OMAP3_GPT10_IRQ, |
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| 90 | .regs = ®s_v1 |
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| 91 | }; |
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| 92 | |
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| 93 | static struct omap_timer *fr_timer = &dm37xx_fr_timer; |
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| 94 | static struct omap_timer *timer = &dm37xx_timer; |
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| 95 | |
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| 96 | #endif |
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| 97 | |
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| 98 | #if IS_AM335X |
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| 99 | |
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| 100 | /* normal timer */ |
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| 101 | static omap_timer_t am335x_timer = { |
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| 102 | .base = AM335X_DMTIMER1_1MS_BASE, |
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| 103 | .irq_nr = AM335X_INT_TINT1_1MS, |
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| 104 | .regs = ®s_v1 |
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| 105 | }; |
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| 106 | |
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| 107 | /* free running timer */ |
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| 108 | static omap_timer_t am335x_fr_timer = { |
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| 109 | .base = AM335X_DMTIMER7_BASE, |
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| 110 | .irq_nr = AM335X_INT_TINT7, |
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| 111 | .regs = ®s_v2 |
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| 112 | }; |
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| 113 | |
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| 114 | static struct omap_timer *fr_timer = &am335x_fr_timer; |
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| 115 | static struct omap_timer *timer = &am335x_timer; |
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| 116 | |
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| 117 | #endif |
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| 118 | |
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| 119 | #if IS_AM335X |
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| 120 | #define FRCLOCK_HZ (16*1500000) |
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| 121 | #endif |
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| 122 | |
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| 123 | #if IS_DM3730 |
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| 124 | #define FRCLOCK_HZ (8*1625000) |
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| 125 | #endif |
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| 126 | |
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| 127 | #ifndef FRCLOCK_HZ |
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| 128 | #error expected IS_AM335X or IS_DM3730 to be defined. |
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| 129 | #endif |
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| 130 | |
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| 131 | static void |
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| 132 | omap3_frclock_init(void) |
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| 133 | { |
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| 134 | uint32_t tisr; |
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| 135 | |
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| 136 | #if IS_DM3730 |
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| 137 | /* Stop timer */ |
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| 138 | mmio_clear(fr_timer->base + fr_timer->regs->TCLR, |
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| 139 | OMAP3_TCLR_ST); |
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| 140 | |
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| 141 | /* Use functional clock source for GPTIMER10 */ |
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| 142 | mmio_set(OMAP3_CM_CLKSEL_CORE, OMAP3_CLKSEL_GPT10); |
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| 143 | #endif |
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| 144 | |
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| 145 | #if IS_AM335X |
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| 146 | /* Disable the module and wait for the module to be disabled */ |
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| 147 | set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK, |
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| 148 | CM_MODULEMODE_DISABLED); |
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| 149 | while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) |
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| 150 | != CM_CLKCTRL_IDLEST_DISABLE); |
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| 151 | |
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| 152 | set32(CLKSEL_TIMER7_CLK, CLKSEL_TIMER7_CLK_SEL_MASK, |
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| 153 | CLKSEL_TIMER7_CLK_SEL_SEL2); |
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| 154 | while ((read32(CLKSEL_TIMER7_CLK) & CLKSEL_TIMER7_CLK_SEL_MASK) |
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| 155 | != CLKSEL_TIMER7_CLK_SEL_SEL2); |
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| 156 | |
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| 157 | /* enable the module and wait for the module to be ready */ |
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| 158 | set32(CM_PER_TIMER7_CLKCTRL, CM_MODULEMODE_MASK, |
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| 159 | CM_MODULEMODE_ENABLE); |
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| 160 | while ((mmio_read(CM_PER_TIMER7_CLKCTRL) & CM_CLKCTRL_IDLEST) |
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| 161 | != CM_CLKCTRL_IDLEST_FUNC); |
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| 162 | |
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| 163 | /* Stop timer */ |
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| 164 | mmio_clear(fr_timer->base + fr_timer->regs->TCLR, |
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| 165 | OMAP3_TCLR_ST); |
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| 166 | #endif |
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| 167 | |
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| 168 | /* Start and auto-reload at 0 */ |
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| 169 | mmio_write(fr_timer->base + fr_timer->regs->TLDR, 0x0); |
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| 170 | mmio_write(fr_timer->base + fr_timer->regs->TCRR, 0x0); |
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| 171 | |
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| 172 | /* Set up overflow interrupt */ |
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| 173 | tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | |
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| 174 | OMAP3_TISR_TCAR_IT_FLAG; |
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| 175 | /* Clear interrupt status */ |
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| 176 | mmio_write(fr_timer->base + fr_timer->regs->TISR, tisr); |
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| 177 | mmio_write(fr_timer->base + fr_timer->regs->TIER, |
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| 178 | OMAP3_TIER_OVF_IT_ENA); |
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| 179 | |
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| 180 | /* Start timer, without prescaler */ |
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| 181 | mmio_set(fr_timer->base + fr_timer->regs->TCLR, |
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| 182 | OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST); |
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| 183 | } |
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| 184 | |
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[75acd9e] | 185 | static uint32_t |
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| 186 | beagle_clock_get_timecount(struct timecounter *tc) |
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[53dd6d61] | 187 | { |
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| 188 | return mmio_read(fr_timer->base + fr_timer->regs->TCRR); |
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| 189 | } |
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| 190 | |
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| 191 | static void |
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| 192 | beagle_clock_initialize(void) |
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| 193 | { |
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| 194 | uint32_t freq = 1000000UL/rtems_configuration_get_microseconds_per_tick(); |
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| 195 | |
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| 196 | /* we only support 1ms resolution */ |
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| 197 | uint32_t tisr; |
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| 198 | #if IS_DM3730 |
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| 199 | /* Stop timer */ |
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| 200 | mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); |
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| 201 | |
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| 202 | /* Use 32 KHz clock source for GPTIMER1 */ |
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| 203 | mmio_clear(OMAP3_CM_CLKSEL_WKUP, OMAP3_CLKSEL_GPT1); |
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| 204 | #endif |
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| 205 | |
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| 206 | #if IS_AM335X |
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| 207 | /* disable the module and wait for the module to be disabled */ |
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| 208 | set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK, |
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| 209 | CM_MODULEMODE_DISABLED); |
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| 210 | while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) |
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| 211 | != CM_CLKCTRL_IDLEST_DISABLE); |
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| 212 | |
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| 213 | set32(CLKSEL_TIMER1MS_CLK, CLKSEL_TIMER1MS_CLK_SEL_MASK, |
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| 214 | CLKSEL_TIMER1MS_CLK_SEL_SEL2); |
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| 215 | while ((read32(CLKSEL_TIMER1MS_CLK) & |
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| 216 | CLKSEL_TIMER1MS_CLK_SEL_MASK) != |
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| 217 | CLKSEL_TIMER1MS_CLK_SEL_SEL2); |
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| 218 | |
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| 219 | /* enable the module and wait for the module to be ready */ |
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| 220 | set32(CM_WKUP_TIMER1_CLKCTRL, CM_MODULEMODE_MASK, |
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| 221 | CM_MODULEMODE_ENABLE); |
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| 222 | while ((mmio_read(CM_WKUP_TIMER1_CLKCTRL) & CM_CLKCTRL_IDLEST) |
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| 223 | != CM_CLKCTRL_IDLEST_FUNC); |
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| 224 | |
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| 225 | /* Stop timer */ |
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| 226 | mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); |
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| 227 | #endif |
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| 228 | |
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| 229 | /* Use 1-ms tick mode for GPTIMER1 TRM 16.2.4.2.1 */ |
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| 230 | mmio_write(timer->base + timer->regs->TPIR, 232000); |
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| 231 | mmio_write(timer->base + timer->regs->TNIR, -768000); |
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| 232 | mmio_write(timer->base + timer->regs->TLDR, |
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| 233 | 0xffffffff - (32768 / freq) + 1); |
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| 234 | mmio_write(timer->base + timer->regs->TCRR, |
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| 235 | 0xffffffff - (32768 / freq) + 1); |
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| 236 | |
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| 237 | /* Set up overflow interrupt */ |
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| 238 | tisr = OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | |
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| 239 | OMAP3_TISR_TCAR_IT_FLAG; |
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| 240 | /* Clear interrupt status */ |
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| 241 | mmio_write(timer->base + timer->regs->TISR, tisr); |
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| 242 | mmio_write(timer->base + timer->regs->TIER, OMAP3_TIER_OVF_IT_ENA); |
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| 243 | |
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| 244 | /* Start timer */ |
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| 245 | mmio_set(timer->base + timer->regs->TCLR, |
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| 246 | OMAP3_TCLR_OVF_TRG | OMAP3_TCLR_AR | OMAP3_TCLR_ST); |
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| 247 | /* also initilize the free runnning timer */ |
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| 248 | omap3_frclock_init(); |
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[13d9029] | 249 | |
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| 250 | #if IS_AM335X |
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| 251 | /* Disable AM335X watchdog */ |
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| 252 | mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0xAAAA); |
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| 253 | while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ; |
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| 254 | mmio_write(AM335X_WDT_BASE+AM335X_WDT_WSPR, 0x5555); |
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| 255 | while(mmio_read(AM335X_WDT_BASE+AM335X_WDT_WWPS) != 0) ; |
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| 256 | #endif |
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| 257 | |
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[75acd9e] | 258 | /* Install timecounter */ \ |
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| 259 | beagle_clock_tc.tc_get_timecount = beagle_clock_get_timecount; |
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| 260 | beagle_clock_tc.tc_counter_mask = 0xffffffff; |
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| 261 | beagle_clock_tc.tc_frequency = FRCLOCK_HZ; |
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| 262 | beagle_clock_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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| 263 | rtems_timecounter_install(&beagle_clock_tc); |
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[53dd6d61] | 264 | } |
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| 265 | |
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| 266 | static void beagle_clock_at_tick(void) |
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| 267 | { |
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| 268 | mmio_write(timer->base + timer->regs->TISR, |
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| 269 | OMAP3_TISR_MAT_IT_FLAG | OMAP3_TISR_OVF_IT_FLAG | |
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| 270 | OMAP3_TISR_TCAR_IT_FLAG); |
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| 271 | } |
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| 272 | |
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| 273 | static rtems_interrupt_handler clock_isr = NULL; |
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| 274 | |
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| 275 | static void beagle_clock_handler_install(rtems_interrupt_handler isr) |
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| 276 | { |
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| 277 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 278 | |
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| 279 | sc = rtems_interrupt_handler_install( |
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| 280 | timer->irq_nr, |
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| 281 | "Clock", |
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| 282 | RTEMS_INTERRUPT_UNIQUE, |
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| 283 | isr, |
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| 284 | NULL |
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| 285 | ); |
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| 286 | |
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| 287 | if (sc != RTEMS_SUCCESSFUL) { |
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| 288 | rtems_fatal_error_occurred(0xdeadbeef); |
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| 289 | } |
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| 290 | clock_isr = isr; |
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| 291 | } |
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| 292 | |
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| 293 | static void beagle_clock_cleanup(void) |
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| 294 | { |
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| 295 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 296 | |
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| 297 | /* Disable timer */ |
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| 298 | mmio_clear(timer->base + timer->regs->TCLR, OMAP3_TCLR_ST); |
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| 299 | |
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| 300 | /* Remove interrupt handler */ |
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| 301 | sc = rtems_interrupt_handler_remove( |
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| 302 | timer->irq_nr, |
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| 303 | clock_isr, |
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| 304 | NULL |
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| 305 | ); |
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| 306 | if (sc != RTEMS_SUCCESSFUL) { |
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| 307 | rtems_fatal_error_occurred(0xdeadbeef); |
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| 308 | } |
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| 309 | clock_isr = NULL; |
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| 310 | |
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| 311 | /* stop frclock */ |
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| 312 | mmio_clear(fr_timer->base + fr_timer->regs->TCLR, OMAP3_TCLR_ST); |
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| 313 | } |
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| 314 | |
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| 315 | #define Clock_driver_support_at_tick() beagle_clock_at_tick() |
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| 316 | #define Clock_driver_support_initialize_hardware() beagle_clock_initialize() |
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| 317 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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| 318 | do { \ |
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| 319 | beagle_clock_handler_install(isr); \ |
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| 320 | old_isr = NULL; \ |
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| 321 | } while (0) |
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| 322 | |
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| 323 | #define Clock_driver_support_shutdown_hardware() beagle_clock_cleanup() |
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| 324 | |
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| 325 | /* Include shared source clock driver code */ |
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| 326 | #include "../../shared/clockdrv_shell.h" |
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