1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bspopts.h> |
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16 | #include <chip.h> |
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17 | #include <include/board_memories.h> |
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18 | |
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19 | #if defined ATSAM_SDRAM_IS42S16100E_7BLI |
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20 | const struct BOARD_Sdram_Config BOARD_Sdram_Config = { |
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21 | /* FIXME: a lot of these values should be calculated using CPU frequency */ |
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22 | .sdramc_tr = 1562, |
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23 | .sdramc_cr = |
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24 | SDRAMC_CR_NC_COL8 /* 8 column bits */ |
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25 | | SDRAMC_CR_NR_ROW11 /* 12 row bits (4K) */ |
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26 | | SDRAMC_CR_CAS_LATENCY3 /* CAS Latency 3 */ |
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27 | | SDRAMC_CR_NB_BANK2 /* 2 banks */ |
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28 | | SDRAMC_CR_DBW /* 16 bit */ |
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29 | | SDRAMC_CR_TWR(5) |
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30 | | SDRAMC_CR_TRC_TRFC(13) /* 63ns min */ |
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31 | | SDRAMC_CR_TRP(5) /* Command period (PRE to ACT) 21 ns min */ |
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32 | | SDRAMC_CR_TRCD(5) /* Active Command to R/W Cmd delay time 21ns min */ |
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33 | | SDRAMC_CR_TRAS(9) /* Command period (ACT to PRE) 42ns min */ |
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34 | | SDRAMC_CR_TXSR(15U), /* Exit self-refresh to active time 70ns Min */ |
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35 | .sdramc_mdr = SDRAMC_MDR_MD_SDRAM, |
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36 | .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2) |
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37 | }; |
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38 | |
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39 | #elif defined ATSAM_SDRAM_IS42S16320F_7BL |
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40 | #define CLOCK_CYCLES_FROM_NS_MAX(ns) \ |
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41 | (((ns) * (BOARD_MCK / 1000ul / 1000ul)) / 1000ul) |
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42 | #define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1) |
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43 | |
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44 | const struct BOARD_Sdram_Config BOARD_Sdram_Config = { |
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45 | /* 8k refresh cycles every 64ms => 7.8125us */ |
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46 | .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul), |
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47 | .sdramc_cr = |
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48 | SDRAMC_CR_NC_COL10 |
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49 | | SDRAMC_CR_NR_ROW13 |
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50 | | SDRAMC_CR_CAS_LATENCY3 |
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51 | | SDRAMC_CR_NB_BANK4 |
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52 | | SDRAMC_CR_DBW |
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53 | /* t_WR = 30ns min (t_RC - t_RP - t_RCD; |
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54 | * see data sheet November 2015 page 55); |
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55 | * add some security margin */ |
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56 | | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40)) |
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57 | | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60)) |
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58 | | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15)) |
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59 | | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15)) |
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60 | | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37)) |
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61 | | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)), |
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62 | .sdramc_mdr = SDRAMC_MDR_MD_SDRAM, |
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63 | .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | |
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64 | SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)) |
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65 | }; |
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66 | |
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67 | #if CLOCK_CYCLES_FROM_NS_MIN(67) > 0xF |
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68 | /* Prevent the fields to be out of range by checking the one with the biggest |
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69 | * value. */ |
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70 | #error SDRAM calculation does not work for the selected clock frequency |
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71 | #endif |
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72 | |
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73 | #else |
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74 | #error SDRAM not supported. |
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75 | #endif |
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