source: rtems/c/src/lib/libbsp/arm/atsam/startup/sdram-config.c @ b9cc5aa

5
Last change on this file since b9cc5aa was b9cc5aa, checked in by Christian Mauderer <Christian.Mauderer@…>, on 08/22/16 at 08:41:33

bsp/atsam: Add SDRAM IS42S16320F-7BL.

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File size: 2.6 KB
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1/*
2 * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bspopts.h>
16#include <chip.h>
17#include <include/board_memories.h>
18
19#if defined ATSAM_SDRAM_IS42S16100E_7BLI
20const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
21  /* FIXME: a lot of these values should be calculated using CPU frequency */
22  .sdramc_tr = 1562,
23  .sdramc_cr =
24      SDRAMC_CR_NC_COL8      /* 8 column bits */
25    | SDRAMC_CR_NR_ROW11     /* 12 row bits (4K) */
26    | SDRAMC_CR_CAS_LATENCY3 /* CAS Latency 3 */
27    | SDRAMC_CR_NB_BANK2     /* 2 banks */
28    | SDRAMC_CR_DBW          /* 16 bit */
29    | SDRAMC_CR_TWR(5)
30    | SDRAMC_CR_TRC_TRFC(13) /* 63ns   min */
31    | SDRAMC_CR_TRP(5)       /* Command period (PRE to ACT) 21 ns min */
32    | SDRAMC_CR_TRCD(5)      /* Active Command to R/W Cmd delay time 21ns min */
33    | SDRAMC_CR_TRAS(9)      /* Command period (ACT to PRE)  42ns min */
34    | SDRAMC_CR_TXSR(15U),   /* Exit self-refresh to active time  70ns Min */
35  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
36  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2)
37};
38
39#elif defined ATSAM_SDRAM_IS42S16320F_7BL
40#define CLOCK_CYCLES_FROM_NS_MAX(ns) \
41    (((ns) * (BOARD_MCK / 1000ul / 1000ul)) / 1000ul)
42#define CLOCK_CYCLES_FROM_NS_MIN(ns) (CLOCK_CYCLES_FROM_NS_MAX(ns) + 1)
43
44const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
45  /* 8k refresh cycles every 64ms => 7.8125us */
46  .sdramc_tr = CLOCK_CYCLES_FROM_NS_MAX(7812ul),
47  .sdramc_cr =
48      SDRAMC_CR_NC_COL10
49    | SDRAMC_CR_NR_ROW13
50    | SDRAMC_CR_CAS_LATENCY3
51    | SDRAMC_CR_NB_BANK4
52    | SDRAMC_CR_DBW
53    /* t_WR = 30ns min (t_RC - t_RP - t_RCD;
54     * see data sheet November 2015 page 55);
55     * add some security margin */
56    | SDRAMC_CR_TWR(CLOCK_CYCLES_FROM_NS_MIN(40))
57    | SDRAMC_CR_TRC_TRFC(CLOCK_CYCLES_FROM_NS_MIN(60))
58    | SDRAMC_CR_TRP(CLOCK_CYCLES_FROM_NS_MIN(15))
59    | SDRAMC_CR_TRCD(CLOCK_CYCLES_FROM_NS_MIN(15))
60    | SDRAMC_CR_TRAS(CLOCK_CYCLES_FROM_NS_MIN(37))
61    | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)),
62  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
63  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
64      SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14))
65};
66
67#if CLOCK_CYCLES_FROM_NS_MIN(67) > 0xF
68  /* Prevent the fields to be out of range by checking the one with the biggest
69   * value. */
70  #error SDRAM calculation does not work for the selected clock frequency
71#endif
72
73#else
74  #error SDRAM not supported.
75#endif
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