1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* Copyright (c) 2016, embedded brains GmbH */ |
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7 | /* */ |
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8 | /* All rights reserved. */ |
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9 | /* */ |
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10 | /* Redistribution and use in source and binary forms, with or without */ |
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11 | /* modification, are permitted provided that the following condition is met: */ |
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12 | /* */ |
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13 | /* - Redistributions of source code must retain the above copyright notice, */ |
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14 | /* this list of conditions and the disclaimer below. */ |
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15 | /* */ |
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16 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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17 | /* this software without specific prior written permission. */ |
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18 | /* */ |
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19 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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20 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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21 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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22 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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23 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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24 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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25 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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26 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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27 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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28 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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29 | /* ---------------------------------------------------------------------------- */ |
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30 | |
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31 | #include <bsp/atsam-clock-config.h> |
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32 | #include <bsp/atsam-spi.h> |
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33 | |
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34 | #include <dev/spi/spi.h> |
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35 | |
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36 | #include <string.h> |
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37 | |
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38 | #define MAX_SPI_FREQUENCY 50000000 |
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39 | |
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40 | typedef struct { |
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41 | spi_bus base; |
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42 | bool msg_cs_change; |
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43 | const spi_ioc_transfer *msg_current; |
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44 | uint32_t msg_todo; |
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45 | int msg_error; |
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46 | rtems_id msg_task; |
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47 | Spid spi; |
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48 | uint32_t dma_tx_channel; |
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49 | uint32_t dma_rx_channel; |
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50 | int transfer_in_progress; |
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51 | bool chip_select_active; |
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52 | } atsam_spi_bus; |
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53 | |
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54 | static void atsam_spi_wakeup_task(atsam_spi_bus *bus) |
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55 | { |
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56 | rtems_status_code sc; |
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57 | |
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58 | sc = rtems_event_transient_send(bus->msg_task); |
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59 | assert(sc == RTEMS_SUCCESSFUL); |
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60 | } |
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61 | |
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62 | static uint8_t atsam_calculate_dlybcs(uint16_t delay_in_us) |
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63 | { |
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64 | return ( |
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65 | (BOARD_MCK / delay_in_us) < 0xFF) ? |
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66 | (BOARD_MCK / delay_in_us) : 0xFF; |
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67 | } |
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68 | |
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69 | static void atsam_set_phase_and_polarity(uint32_t mode, uint32_t *csr) |
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70 | { |
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71 | uint32_t mode_mask = mode & SPI_MODE_3; |
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72 | |
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73 | switch(mode_mask) { |
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74 | case SPI_MODE_0: |
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75 | *csr |= SPI_CSR_NCPHA; |
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76 | break; |
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77 | case SPI_MODE_1: |
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78 | break; |
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79 | case SPI_MODE_2: |
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80 | *csr |= SPI_CSR_NCPHA; |
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81 | *csr |= SPI_CSR_CPOL; |
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82 | break; |
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83 | case SPI_MODE_3: |
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84 | *csr |= SPI_CSR_CPOL; |
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85 | break; |
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86 | } |
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87 | *csr |= SPI_CSR_CSAAT; |
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88 | } |
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89 | |
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90 | static void atsam_configure_spi(atsam_spi_bus *bus) |
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91 | { |
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92 | uint8_t delay_cs; |
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93 | uint32_t csr = 0; |
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94 | |
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95 | delay_cs = atsam_calculate_dlybcs(bus->base.delay_usecs); |
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96 | |
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97 | SPID_Configure( |
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98 | &bus->spi, |
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99 | bus->spi.pSpiHw, |
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100 | bus->spi.spiId, |
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101 | (SPI_MR_DLYBCS(delay_cs) | |
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102 | SPI_MR_MSTR | |
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103 | SPI_MR_MODFDIS | |
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104 | SPI_PCS(bus->base.cs)), |
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105 | &XDMAD_Instance |
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106 | ); |
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107 | |
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108 | csr = |
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109 | SPI_DLYBCT(1000, BOARD_MCK) | |
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110 | SPI_DLYBS(1000, BOARD_MCK) | |
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111 | SPI_SCBR(bus->base.speed_hz, BOARD_MCK) | |
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112 | SPI_CSR_BITS(bus->base.bits_per_word - 8); |
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113 | |
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114 | atsam_set_phase_and_polarity(bus->base.mode, &csr); |
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115 | |
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116 | SPI_ConfigureNPCS(bus->spi.pSpiHw, bus->base.cs, csr); |
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117 | } |
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118 | |
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119 | static void atsam_spi_start_dma_transfer( |
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120 | atsam_spi_bus *bus, |
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121 | const spi_ioc_transfer *msg |
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122 | ) |
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123 | { |
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124 | Xdmac *pXdmac = XDMAC; |
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125 | |
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126 | XDMAC_SetDestinationAddr(pXdmac, bus->dma_rx_channel, (uint32_t)msg->rx_buf); |
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127 | XDMAC_SetSourceAddr(pXdmac, bus->dma_tx_channel, (uint32_t)msg->tx_buf); |
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128 | XDMAC_SetMicroblockControl(pXdmac, bus->dma_rx_channel, msg->len); |
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129 | XDMAC_SetMicroblockControl(pXdmac, bus->dma_tx_channel, msg->len); |
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130 | XDMAC_StartTransfer(pXdmac, bus->dma_rx_channel); |
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131 | XDMAC_StartTransfer(pXdmac, bus->dma_tx_channel); |
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132 | } |
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133 | |
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134 | static void atsam_spi_do_transfer( |
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135 | atsam_spi_bus *bus, |
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136 | const spi_ioc_transfer *msg |
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137 | ) |
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138 | { |
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139 | if (!bus->chip_select_active){ |
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140 | Spi *pSpiHw = bus->spi.pSpiHw; |
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141 | |
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142 | bus->chip_select_active = true; |
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143 | |
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144 | SPI_ChipSelect(pSpiHw, 1 << msg->cs); |
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145 | SPI_Enable(pSpiHw); |
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146 | } |
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147 | |
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148 | atsam_spi_start_dma_transfer(bus, msg); |
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149 | } |
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150 | |
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151 | static int atsam_check_configure_spi(atsam_spi_bus *bus, const spi_ioc_transfer *msg) |
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152 | { |
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153 | if ( |
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154 | msg->mode != bus->base.mode |
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155 | || msg->speed_hz != bus->base.speed_hz |
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156 | || msg->bits_per_word != bus->base.bits_per_word |
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157 | || msg->cs != bus->base.cs |
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158 | || msg->delay_usecs != bus->base.delay_usecs |
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159 | ) { |
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160 | if ( |
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161 | msg->bits_per_word < 8 |
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162 | || msg->bits_per_word > 16 |
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163 | || msg->mode > 3 |
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164 | || msg->speed_hz > bus->base.max_speed_hz |
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165 | ) { |
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166 | return -EINVAL; |
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167 | } |
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168 | |
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169 | bus->base.mode = msg->mode; |
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170 | bus->base.speed_hz = msg->speed_hz; |
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171 | bus->base.bits_per_word = msg->bits_per_word; |
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172 | bus->base.cs = msg->cs; |
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173 | bus->base.delay_usecs = msg->delay_usecs; |
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174 | atsam_configure_spi(bus); |
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175 | } |
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176 | |
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177 | return 0; |
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178 | } |
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179 | |
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180 | static void atsam_spi_setup_transfer(atsam_spi_bus *bus) |
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181 | { |
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182 | uint32_t msg_todo = bus->msg_todo; |
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183 | |
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184 | bus->transfer_in_progress = 2; |
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185 | |
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186 | if (bus->msg_cs_change) { |
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187 | bus->chip_select_active = false; |
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188 | SPI_ReleaseCS(bus->spi.pSpiHw); |
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189 | SPI_Disable(bus->spi.pSpiHw); |
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190 | } |
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191 | |
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192 | if (msg_todo > 0) { |
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193 | const spi_ioc_transfer *msg = bus->msg_current; |
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194 | int error; |
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195 | |
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196 | bus->msg_cs_change = msg->cs_change; |
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197 | bus->msg_current = msg + 1; |
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198 | bus->msg_todo = msg_todo - 1; |
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199 | |
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200 | error = atsam_check_configure_spi(bus, msg); |
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201 | if (error == 0) { |
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202 | atsam_spi_do_transfer(bus, msg); |
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203 | } else { |
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204 | bus->msg_error = error; |
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205 | atsam_spi_wakeup_task(bus); |
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206 | } |
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207 | } else { |
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208 | atsam_spi_wakeup_task(bus); |
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209 | } |
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210 | } |
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211 | |
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212 | static void atsam_spi_dma_callback(uint32_t channel, void *arg) |
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213 | { |
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214 | atsam_spi_bus *bus = (atsam_spi_bus *)arg; |
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215 | |
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216 | --bus->transfer_in_progress; |
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217 | |
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218 | if (bus->transfer_in_progress == 0) { |
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219 | atsam_spi_setup_transfer(bus); |
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220 | } |
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221 | } |
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222 | |
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223 | static int atsam_spi_transfer( |
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224 | spi_bus *base, |
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225 | const spi_ioc_transfer *msgs, |
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226 | uint32_t msg_count |
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227 | ) |
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228 | { |
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229 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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230 | |
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231 | bus->msg_cs_change = false; |
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232 | bus->msg_current = &msgs[0]; |
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233 | bus->msg_todo = msg_count; |
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234 | bus->msg_error = 0; |
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235 | bus->msg_task = rtems_task_self(); |
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236 | atsam_spi_setup_transfer(bus); |
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237 | rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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238 | return bus->msg_error; |
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239 | } |
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240 | |
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241 | |
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242 | static void atsam_spi_destroy(spi_bus *base) |
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243 | { |
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244 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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245 | eXdmadRC rc; |
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246 | |
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247 | rc = XDMAD_SetCallback( |
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248 | bus->spi.pXdmad, |
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249 | bus->dma_rx_channel, |
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250 | XDMAD_DoNothingCallback, |
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251 | NULL |
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252 | ); |
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253 | assert(rc == XDMAD_OK); |
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254 | |
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255 | rc = XDMAD_SetCallback( |
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256 | bus->spi.pXdmad, |
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257 | bus->dma_tx_channel, |
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258 | XDMAD_DoNothingCallback, |
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259 | NULL |
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260 | ); |
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261 | assert(rc == XDMAD_OK); |
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262 | |
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263 | XDMAD_FreeChannel(bus->spi.pXdmad, bus->dma_rx_channel); |
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264 | XDMAD_FreeChannel(bus->spi.pXdmad, bus->dma_tx_channel); |
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265 | |
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266 | SPI_Disable(bus->spi.pSpiHw); |
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267 | PMC_DisablePeripheral(bus->spi.spiId); |
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268 | |
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269 | spi_bus_destroy_and_free(&bus->base); |
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270 | } |
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271 | |
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272 | static int atsam_spi_setup(spi_bus *base) |
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273 | { |
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274 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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275 | |
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276 | if ( |
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277 | bus->base.speed_hz > MAX_SPI_FREQUENCY || |
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278 | bus->base.bits_per_word < 8 || |
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279 | bus->base.bits_per_word > 16 |
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280 | ) { |
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281 | return -EINVAL; |
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282 | } |
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283 | atsam_configure_spi(bus); |
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284 | return 0; |
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285 | } |
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286 | |
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287 | static void atsam_spi_init_xdma(atsam_spi_bus *bus) |
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288 | { |
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289 | sXdmadCfg cfg; |
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290 | uint32_t xdmaInt; |
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291 | uint8_t channel; |
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292 | eXdmadRC rc; |
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293 | |
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294 | bus->dma_tx_channel = XDMAD_AllocateChannel( |
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295 | bus->spi.pXdmad, |
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296 | XDMAD_TRANSFER_MEMORY, |
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297 | bus->spi.spiId |
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298 | ); |
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299 | assert(bus->dma_tx_channel != XDMAD_ALLOC_FAILED); |
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300 | |
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301 | bus->dma_rx_channel = XDMAD_AllocateChannel( |
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302 | bus->spi.pXdmad, |
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303 | bus->spi.spiId, |
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304 | XDMAD_TRANSFER_MEMORY |
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305 | ); |
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306 | assert(bus->dma_rx_channel != XDMAD_ALLOC_FAILED); |
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307 | |
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308 | rc = XDMAD_SetCallback( |
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309 | bus->spi.pXdmad, |
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310 | bus->dma_rx_channel, |
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311 | atsam_spi_dma_callback, |
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312 | bus |
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313 | ); |
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314 | assert(rc == XDMAD_OK); |
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315 | |
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316 | rc = XDMAD_SetCallback( |
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317 | bus->spi.pXdmad, |
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318 | bus->dma_tx_channel, |
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319 | atsam_spi_dma_callback, |
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320 | bus |
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321 | ); |
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322 | assert(rc == XDMAD_OK); |
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323 | |
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324 | rc = XDMAD_PrepareChannel(bus->spi.pXdmad, bus->dma_rx_channel); |
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325 | assert(rc == XDMAD_OK); |
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326 | |
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327 | rc = XDMAD_PrepareChannel(bus->spi.pXdmad, bus->dma_tx_channel); |
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328 | assert(rc == XDMAD_OK); |
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329 | |
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330 | /* Put all interrupts on for non LLI list setup of DMA */ |
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331 | xdmaInt = ( |
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332 | XDMAC_CIE_BIE | |
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333 | XDMAC_CIE_DIE | |
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334 | XDMAC_CIE_FIE | |
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335 | XDMAC_CIE_RBIE | |
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336 | XDMAC_CIE_WBIE | |
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337 | XDMAC_CIE_ROIE); |
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338 | |
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339 | /* Setup RX */ |
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340 | memset(&cfg, 0, sizeof(cfg)); |
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341 | channel = XDMAIF_Get_ChannelNumber(bus->spi.spiId, XDMAD_TRANSFER_RX); |
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342 | cfg.mbr_sa = (uint32_t)&bus->spi.pSpiHw->SPI_RDR; |
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343 | cfg.mbr_cfg = |
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344 | XDMAC_CC_TYPE_PER_TRAN | |
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345 | XDMAC_CC_MBSIZE_SINGLE | |
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346 | XDMAC_CC_DSYNC_PER2MEM | |
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347 | XDMAC_CC_CSIZE_CHK_1 | |
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348 | XDMAC_CC_DWIDTH_BYTE | |
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349 | XDMAC_CC_SIF_AHB_IF1 | |
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350 | XDMAC_CC_DIF_AHB_IF1 | |
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351 | XDMAC_CC_SAM_FIXED_AM | |
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352 | XDMAC_CC_DAM_INCREMENTED_AM | |
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353 | XDMAC_CC_PERID(channel); |
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354 | rc = XDMAD_ConfigureTransfer( |
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355 | bus->spi.pXdmad, |
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356 | bus->dma_rx_channel, |
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357 | &cfg, |
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358 | 0, |
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359 | 0, |
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360 | xdmaInt |
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361 | ); |
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362 | assert(rc == XDMAD_OK); |
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363 | |
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364 | /* Setup TX */ |
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365 | memset(&cfg, 0, sizeof(cfg)); |
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366 | channel = XDMAIF_Get_ChannelNumber(bus->spi.spiId, XDMAD_TRANSFER_TX); |
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367 | cfg.mbr_da = (uint32_t)&bus->spi.pSpiHw->SPI_TDR; |
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368 | cfg.mbr_cfg = |
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369 | XDMAC_CC_TYPE_PER_TRAN | |
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370 | XDMAC_CC_MBSIZE_SINGLE | |
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371 | XDMAC_CC_DSYNC_MEM2PER | |
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372 | XDMAC_CC_CSIZE_CHK_1 | |
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373 | XDMAC_CC_DWIDTH_BYTE | |
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374 | XDMAC_CC_SIF_AHB_IF1 | |
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375 | XDMAC_CC_DIF_AHB_IF1 | |
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376 | XDMAC_CC_SAM_INCREMENTED_AM | |
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377 | XDMAC_CC_DAM_FIXED_AM | |
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378 | XDMAC_CC_PERID(channel); |
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379 | rc = XDMAD_ConfigureTransfer( |
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380 | bus->spi.pXdmad, |
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381 | bus->dma_tx_channel, |
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382 | &cfg, |
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383 | 0, |
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384 | 0, |
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385 | xdmaInt |
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386 | ); |
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387 | assert(rc == XDMAD_OK); |
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388 | } |
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389 | |
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390 | int spi_bus_register_atsam( |
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391 | const char *bus_path, |
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392 | uint8_t spi_peripheral_id, |
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393 | Spi *spi_regs, |
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394 | const Pin *pins, |
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395 | size_t pin_count |
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396 | ) |
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397 | { |
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398 | atsam_spi_bus *bus; |
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399 | |
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400 | bus = (atsam_spi_bus *) spi_bus_alloc_and_init(sizeof(*bus)); |
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401 | if (bus == NULL) { |
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402 | return -1; |
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403 | } |
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404 | |
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405 | bus->base.transfer = atsam_spi_transfer; |
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406 | bus->base.destroy = atsam_spi_destroy; |
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407 | bus->base.setup = atsam_spi_setup; |
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408 | bus->base.max_speed_hz = MAX_SPI_FREQUENCY; |
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409 | bus->base.bits_per_word = 8; |
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410 | bus->base.speed_hz = bus->base.max_speed_hz; |
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411 | bus->base.delay_usecs = 1; |
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412 | bus->base.cs = 1; |
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413 | bus->spi.spiId = spi_peripheral_id; |
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414 | bus->spi.pSpiHw = spi_regs; |
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415 | |
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416 | PIO_Configure(pins, pin_count); |
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417 | PMC_EnablePeripheral(spi_peripheral_id); |
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418 | atsam_configure_spi(bus); |
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419 | atsam_spi_init_xdma(bus); |
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420 | |
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421 | return spi_bus_register(&bus->base, bus_path); |
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422 | } |
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