1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /** |
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31 | * \addtogroup qspi_dma_module QSPI xDMA driver |
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32 | * \ingroup peripherals_module |
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33 | * |
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34 | * |
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35 | */ |
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36 | |
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37 | /** |
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38 | * \file |
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39 | * |
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40 | * Implementation for the SPI Flash with xDMA driver. |
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41 | * |
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42 | */ |
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43 | |
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44 | |
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45 | /*---------------------------------------------------------------------------- |
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46 | * Headers |
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47 | *----------------------------------------------------------------------------*/ |
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48 | |
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49 | #include "chip.h" |
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50 | |
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51 | /*---------------------------------------------------------------------------- |
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52 | * Definitions |
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53 | *----------------------------------------------------------------------------*/ |
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54 | |
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55 | /** xDMA support */ |
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56 | |
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57 | /** xDMA Link List size for SPI transmission*/ |
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58 | #define DMA_QSPI_LLI 2 |
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59 | |
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60 | /*----------------------------------------------------------------------------- |
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61 | * QSPI DMA Local functions |
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62 | *----------------------------------------------------------------------------*/ |
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63 | |
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64 | /** |
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65 | * \brief SPI xDMA Rx callback |
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66 | * Invoked on SPi DMA reception done. |
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67 | * \param channel DMA channel. |
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68 | * \param pArg Pointer to callback argument - Pointer to Spid instance. |
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69 | */ |
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70 | static void QSPID_Spi_Cb(uint32_t channel, QspiDma_t *pArg) |
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71 | { |
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72 | Qspi *pQspiHw = pArg->Qspid.pQspiHw; |
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73 | |
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74 | if (channel != pArg->RxChNum) |
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75 | return; |
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76 | |
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77 | /* Release the semaphore */ |
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78 | ReleaseMutex(pArg->progress); |
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79 | QSPI_EndTransfer(pQspiHw); |
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80 | SCB_InvalidateDCache_by_Addr((uint32_t *)pArg->Qspid.qspiBuffer.pDataRx, |
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81 | pArg->Qspid.qspiBuffer.RxDataSize); |
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82 | memory_sync(); |
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83 | } |
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84 | |
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85 | |
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86 | /** |
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87 | * \brief QSPI xDMA Tx callback |
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88 | * Invoked on QSPi DMA Write done. |
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89 | * \param channel DMA channel. |
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90 | * \param pArg Pointer to callback argument - Pointer to Spid instance. |
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91 | */ |
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92 | static void QSPID_qspiTx_Cb(uint32_t channel, QspiDma_t *pArg) |
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93 | { |
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94 | Qspi *pQspiHw = pArg->Qspid.pQspiHw; |
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95 | |
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96 | if (channel != pArg->TxChNum) |
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97 | return; |
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98 | |
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99 | /* Release the semaphore */ |
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100 | ReleaseMutex(pArg->progress); |
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101 | QSPI_EndTransfer(pQspiHw); |
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102 | |
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103 | while (!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst)); |
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104 | |
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105 | memory_sync(); |
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106 | } |
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107 | |
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108 | |
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109 | /** |
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110 | * \brief QSPI xDMA Rx callback |
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111 | * Invoked on SPi DMA reception done. |
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112 | * \param channel DMA channel. |
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113 | * \param pArg Pointer to callback argument - Pointer to Spid instance. |
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114 | */ |
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115 | static void QSPID_qspiRx_Cb(uint32_t channel, QspiDma_t *pArg) |
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116 | { |
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117 | Qspi *pQspiHw = pArg->Qspid.pQspiHw; |
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118 | |
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119 | if (channel != pArg->RxChNum) |
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120 | return; |
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121 | |
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122 | /* Release the semaphore */ |
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123 | ReleaseMutex(pArg->progress); |
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124 | QSPI_EndTransfer(pQspiHw); |
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125 | |
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126 | while (!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst)); |
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127 | |
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128 | SCB_InvalidateDCache_by_Addr((uint32_t *)pArg->Qspid.qspiBuffer.pDataRx, |
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129 | pArg->Qspid.qspiBuffer.RxDataSize); |
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130 | memory_sync(); |
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131 | } |
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132 | |
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133 | /** |
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134 | * \brief Configures the DMA for QSPI |
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135 | * |
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136 | * \param pQspidma Pointer to QSPI DMA structure |
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137 | * \param Addr Address to Read or write of QSPI flash memory |
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138 | * \param pBuffer Pointer input/output buffer |
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139 | * \param ReadWrite Read or write memory flag |
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140 | * \returns 0 if the dma multibuffer configuration successfully; otherwise returns |
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141 | * QSPID_ERROR_XXX. |
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142 | */ |
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143 | static uint8_t QSPID_configureQpsiDma(QspiDma_t *pQspidma, uint32_t Addr, |
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144 | QspiBuffer_t *pBuffer, Access_t const ReadWrite) |
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145 | { |
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146 | sXdmadCfg xdmadCfg, xdmadRxCfg, xdmadTxCfg; |
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147 | uint8_t chanNum; |
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148 | uint8_t qspi_id = pQspidma->Qspid.qspiId; |
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149 | Qspi *pQspiHw = pQspidma->Qspid.pQspiHw; |
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150 | uint32_t xdmaCndc, xdmaInt, BurstSize, ChannelWidth; |
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151 | |
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152 | |
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153 | /* Setup DMA for QSPI */ |
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154 | |
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155 | if (pQspidma->Qspid.qspiMode == QSPI_MR_SMM_SPI) { |
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156 | // SPI mode |
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157 | /* SPI TX DMA config */ |
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158 | xdmadTxCfg.mbr_sa = (uint32_t)pBuffer->pDataTx; |
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159 | xdmadTxCfg.mbr_da = (uint32_t)&pQspiHw->QSPI_TDR; |
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160 | xdmadTxCfg.mbr_ubc = (pBuffer->TxDataSize); |
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161 | |
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162 | xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | |
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163 | XDMAC_CC_MBSIZE_SINGLE | |
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164 | XDMAC_CC_DSYNC_MEM2PER | |
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165 | XDMAC_CC_CSIZE_CHK_1 | |
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166 | XDMAC_CC_DWIDTH_BYTE | |
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167 | XDMAC_CC_SIF_AHB_IF0 | |
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168 | XDMAC_CC_DIF_AHB_IF1 | |
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169 | XDMAC_CC_SAM_INCREMENTED_AM | |
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170 | XDMAC_CC_DAM_FIXED_AM | |
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171 | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber |
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172 | (qspi_id, XDMAD_TRANSFER_TX)); |
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173 | |
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174 | xdmadTxCfg.mbr_bc = 0; |
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175 | xdmadTxCfg.mbr_sus = 0; |
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176 | xdmadTxCfg.mbr_dus = 0; |
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177 | |
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178 | /* SPI RX DMA config */ |
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179 | |
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180 | xdmadRxCfg.mbr_da = (uint32_t)pBuffer->pDataRx; |
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181 | xdmadRxCfg.mbr_sa = (uint32_t)&pQspiHw->QSPI_RDR; |
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182 | xdmadRxCfg.mbr_ubc = (pBuffer->RxDataSize); |
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183 | xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | |
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184 | XDMAC_CC_MBSIZE_SINGLE | |
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185 | XDMAC_CC_DSYNC_PER2MEM | |
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186 | XDMAC_CC_CSIZE_CHK_1 | |
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187 | XDMAC_CC_DWIDTH_BYTE | |
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188 | XDMAC_CC_SIF_AHB_IF1 | |
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189 | XDMAC_CC_DIF_AHB_IF0 | |
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190 | XDMAC_CC_SAM_FIXED_AM | |
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191 | XDMAC_CC_DAM_INCREMENTED_AM | |
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192 | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber |
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193 | (qspi_id, XDMAD_TRANSFER_RX)); |
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194 | |
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195 | xdmadRxCfg.mbr_bc = 0; |
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196 | xdmadRxCfg.mbr_sus = 0; |
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197 | xdmadRxCfg.mbr_dus = 0; |
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198 | xdmaCndc = 0; |
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199 | /* Put all interrupts on for non LLI list setup of DMA */ |
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200 | xdmaInt = (XDMAC_CIE_BIE | |
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201 | XDMAC_CIE_RBIE | |
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202 | XDMAC_CIE_WBIE | |
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203 | XDMAC_CIE_ROIE); |
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204 | |
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205 | memory_barrier(); |
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206 | |
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207 | if (XDMAD_ConfigureTransfer |
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208 | (pQspidma->pXdmad, pQspidma->RxChNum, &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) |
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209 | return QSPID_ERROR; |
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210 | |
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211 | if (XDMAD_ConfigureTransfer |
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212 | (pQspidma->pXdmad, pQspidma->TxChNum, &xdmadTxCfg, xdmaCndc, 0, xdmaInt)) |
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213 | return QSPID_ERROR; |
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214 | |
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215 | return 0; |
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216 | |
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217 | } else { |
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218 | if (ReadWrite == WriteAccess) { |
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219 | xdmadCfg.mbr_sa = (uint32_t)pBuffer->pDataTx; |
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220 | xdmadCfg.mbr_da = (uint32_t)(QSPIMEM_ADDR | Addr); |
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221 | xdmadCfg.mbr_ubc = (pBuffer->TxDataSize); |
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222 | chanNum = pQspidma->TxChNum; |
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223 | ChannelWidth = XDMAC_CC_DWIDTH_BYTE; |
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224 | BurstSize = XDMAC_CC_MBSIZE_SIXTEEN; |
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225 | } else if (ReadWrite == ReadAccess) { |
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226 | xdmadCfg.mbr_da = (uint32_t)pBuffer->pDataRx; |
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227 | xdmadCfg.mbr_sa = (uint32_t)(QSPIMEM_ADDR | Addr); |
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228 | xdmadCfg.mbr_ubc = ((pBuffer->RxDataSize >> 2)); |
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229 | chanNum = pQspidma->RxChNum; |
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230 | ChannelWidth = XDMAC_CC_DWIDTH_WORD; |
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231 | BurstSize = XDMAC_CC_MBSIZE_SIXTEEN; |
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232 | } else { |
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233 | TRACE_ERROR(" QSPI error \n\r"); |
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234 | return 1; |
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235 | } |
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236 | |
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237 | xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN | |
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238 | XDMAC_CC_MEMSET_NORMAL_MODE | |
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239 | BurstSize | |
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240 | ChannelWidth | |
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241 | XDMAC_CC_SIF_AHB_IF1 | |
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242 | XDMAC_CC_DIF_AHB_IF1 | |
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243 | XDMAC_CC_SAM_INCREMENTED_AM | |
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244 | XDMAC_CC_DAM_INCREMENTED_AM; |
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245 | |
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246 | xdmadCfg.mbr_bc = 0; |
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247 | xdmadCfg.mbr_sus = 0; |
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248 | xdmadCfg.mbr_dus = 0; |
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249 | |
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250 | xdmaCndc = 0; |
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251 | |
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252 | |
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253 | /* Put all interrupts on for non LLI list setup of DMA */ |
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254 | xdmaInt = (XDMAC_CIE_BIE | |
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255 | XDMAC_CIE_RBIE | |
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256 | XDMAC_CIE_WBIE | |
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257 | XDMAC_CIE_ROIE); |
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258 | |
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259 | memory_barrier(); |
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260 | |
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261 | if (XDMAD_ConfigureTransfer(pQspidma->pXdmad, chanNum, &xdmadCfg, xdmaCndc, 0, |
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262 | xdmaInt)) |
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263 | return QSPID_ERROR; |
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264 | |
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265 | return 0; |
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266 | } |
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267 | } |
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268 | |
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269 | /*---------------------------------------------------------------------------- |
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270 | * Exported functions |
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271 | *----------------------------------------------------------------------------*/ |
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272 | /** |
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273 | * \brief Initializes the pQspidma structure and the corresponding QSPI & DMA . |
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274 | * hardware select value. |
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275 | * |
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276 | * \param pQspidma Pointer to a QspiDma_t instance. |
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277 | * \param Mode Associated SPI peripheral. |
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278 | * \param dwConf QSPI peripheral configuration. |
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279 | * \param pXdmad Pointer to a Xdmad instance. |
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280 | */ |
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281 | uint32_t QSPID_Configure(QspiDma_t *pQspidma, QspiMode_t Mode, |
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282 | uint32_t dwConf, sXdmad *pXdmad) |
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283 | { |
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284 | /* Initialize the QSPI structure */ |
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285 | |
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286 | QSPI_ConfigureInterface(&pQspidma->Qspid, Mode, dwConf); |
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287 | |
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288 | pQspidma->Qspid.qspiCommand.Instruction = 0; |
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289 | pQspidma->Qspid.qspiCommand.Option = 0; |
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290 | |
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291 | pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; |
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292 | pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; |
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293 | |
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294 | pQspidma->pXdmad = pXdmad; |
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295 | |
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296 | /* XDMA Driver initialize */ |
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297 | XDMAD_Initialize(pQspidma->pXdmad, 0); |
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298 | |
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299 | /* Configure and enable interrupt */ |
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300 | NVIC_ClearPendingIRQ(XDMAC_IRQn); |
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301 | NVIC_SetPriority(XDMAC_IRQn , 1); |
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302 | NVIC_EnableIRQ(XDMAC_IRQn); |
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303 | |
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304 | |
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305 | return QSPI_SUCCESS; |
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306 | } |
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307 | |
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308 | |
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309 | |
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310 | /** |
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311 | * \brief Enables a QSPI Rx channel. This function will allocate a dma Rx |
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312 | * channel for QSPI |
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313 | * |
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314 | * \param pQspidma Pointer to a Spid instance. |
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315 | |
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316 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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317 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is not |
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318 | * valid. |
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319 | */ |
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320 | uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma) |
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321 | { |
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322 | static uint16_t DmaChannel; |
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323 | |
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324 | /* Try to get the semaphore */ |
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325 | if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED) |
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326 | return QSPID_ERROR_LOCK; |
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327 | |
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328 | /* Allocate a DMA channel */ |
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329 | DmaChannel = XDMAD_AllocateChannel( |
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330 | pQspidma->pXdmad, XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY); |
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331 | |
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332 | if (DmaChannel == XDMAD_ALLOC_FAILED) |
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333 | return QSPID_ERROR; |
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334 | |
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335 | pQspidma->RxChNum = DmaChannel; |
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336 | /* Setup callbacks*/ |
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337 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, |
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338 | (XdmadTransferCallback)QSPID_qspiRx_Cb, pQspidma); |
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339 | |
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340 | if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->RxChNum)) |
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341 | return QSPID_ERROR; |
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342 | |
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343 | return 0; |
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344 | } |
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345 | |
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346 | |
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347 | /** |
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348 | * \brief Enables a QSPI Tx channel. This function will allocate a dma Tx |
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349 | * channel for QSPI |
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350 | * |
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351 | * \param pQspidma Pointer to a Spid instance. |
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352 | |
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353 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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354 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
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355 | * not valid. |
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356 | */ |
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357 | uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma) |
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358 | { |
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359 | static uint16_t DmaChannel; |
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360 | |
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361 | /* Try to get the semaphore */ |
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362 | if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED) |
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363 | return QSPID_ERROR_LOCK; |
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364 | |
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365 | /* Allocate a DMA channel */ |
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366 | DmaChannel = XDMAD_AllocateChannel(pQspidma->pXdmad, |
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367 | XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY); |
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368 | |
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369 | if (DmaChannel == XDMAD_ALLOC_FAILED) |
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370 | return QSPID_ERROR; |
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371 | |
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372 | pQspidma->TxChNum = DmaChannel; |
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373 | /* Setup callbacks */ |
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374 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, |
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375 | (XdmadTransferCallback)QSPID_qspiTx_Cb, pQspidma); |
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376 | |
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377 | if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->TxChNum)) |
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378 | return QSPID_ERROR; |
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379 | |
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380 | return 0; |
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381 | } |
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382 | |
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383 | |
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384 | /** |
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385 | * \brief Enables a QSPI SPI Rx channel. This function will allocate a dma |
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386 | * Rx channel for QSPI SPI mode |
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387 | * |
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388 | * \param pQspidma Pointer to a Spid instance. |
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389 | |
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390 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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391 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
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392 | * not valid. |
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393 | */ |
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394 | uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma) |
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395 | { |
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396 | static uint16_t DmaChannel; |
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397 | |
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398 | /* Try to get the semaphore */ |
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399 | if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED) |
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400 | return QSPID_ERROR_LOCK; |
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401 | |
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402 | /* Try to get the semaphore */ |
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403 | if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED) |
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404 | return QSPID_ERROR_LOCK; |
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405 | |
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406 | /* Allocate a DMA channel */ |
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407 | DmaChannel = XDMAD_AllocateChannel |
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408 | (pQspidma->pXdmad, pQspidma->Qspid.qspiId, XDMAD_TRANSFER_MEMORY); |
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409 | |
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410 | if (DmaChannel == XDMAD_ALLOC_FAILED) |
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411 | return QSPID_ERROR; |
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412 | |
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413 | pQspidma->RxChNum = DmaChannel; |
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414 | |
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415 | /* Allocate a DMA channel */ |
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416 | DmaChannel = XDMAD_AllocateChannel(pQspidma->pXdmad, |
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417 | XDMAD_TRANSFER_MEMORY, pQspidma->Qspid.qspiId); |
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418 | |
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419 | if (DmaChannel == XDMAD_ALLOC_FAILED) |
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420 | return QSPID_ERROR; |
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421 | |
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422 | pQspidma->TxChNum = DmaChannel; |
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423 | |
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424 | /* Setup callbacks*/ |
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425 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, |
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426 | (XdmadTransferCallback)QSPID_Spi_Cb, pQspidma); |
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427 | |
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428 | if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->RxChNum)) |
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429 | return QSPID_ERROR; |
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430 | |
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431 | /* Setup callbacks for SPI0/1 TX (ignored) */ |
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432 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL); |
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433 | |
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434 | if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->TxChNum)) |
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435 | return QSPID_ERROR; |
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436 | |
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437 | return 0; |
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438 | } |
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439 | |
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440 | |
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441 | /** |
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442 | * \brief Disables a QSPI Rx channel. This function will de-allocate previous |
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443 | * allocated dma Rx channel for QSPI |
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444 | * |
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445 | * \param pQspidma Pointer to a Spid instance. |
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446 | |
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447 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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448 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
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449 | * not valid. |
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450 | */ |
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451 | uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma) |
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452 | { |
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453 | |
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454 | XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum); |
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455 | XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum); |
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456 | |
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457 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL); |
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458 | |
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459 | |
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460 | /* Free allocated DMA channel for QSPI RX. */ |
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461 | XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->RxChNum); |
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462 | |
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463 | pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; |
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464 | |
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465 | return 0; |
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466 | } |
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467 | |
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468 | |
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469 | |
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470 | /** |
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471 | * \brief Disables a QSPI Tx channel. This function will de-allocate previous |
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472 | * allocated dma Tx channel for QSPI |
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473 | * |
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474 | * \param pQspidma Pointer to a Spid instance. |
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475 | |
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476 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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477 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
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478 | * not valid. |
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479 | */ |
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480 | uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma) |
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481 | { |
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482 | |
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483 | XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->TxChNum); |
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484 | XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum); |
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485 | |
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486 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL); |
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487 | |
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488 | /* Free allocated DMA channel for QSPI TX. */ |
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489 | XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->TxChNum); |
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490 | |
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491 | pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; |
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492 | |
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493 | return 0; |
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494 | } |
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495 | |
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496 | |
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497 | /** |
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498 | * \brief Disables a QSPI SPI Rx and Tx channels. This function will |
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499 | * de-allocate privious allocated dma Rx, Txchannel for QSPI in SPI mode |
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500 | * |
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501 | * \param pQspidma Pointer to a Spid instance. |
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502 | |
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503 | * \returns 0 if the transfer has been started successfully; otherwise returns |
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504 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
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505 | * not valid. |
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506 | */ |
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507 | uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma) |
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508 | { |
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509 | |
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510 | XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum); |
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511 | //XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->TxChNum); |
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512 | XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum); |
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513 | XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum); |
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514 | |
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515 | XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL); |
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516 | |
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517 | /* Free allocated DMA channel for QSPI RX. */ |
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518 | XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->RxChNum); |
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519 | |
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520 | XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->TxChNum); |
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521 | |
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522 | pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; |
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523 | pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; |
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524 | |
---|
525 | return 0; |
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526 | } |
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527 | |
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528 | |
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529 | /** |
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530 | * \brief Starts a QSPI read or write operation. |
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531 | * |
---|
532 | * \param pQspidma Pointer to a Qspid instance. |
---|
533 | * \param ReadWrite Defines the memory access type |
---|
534 | * \returns 0 if the transfer has been started successfully; otherwise returns |
---|
535 | * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is |
---|
536 | * not valid. |
---|
537 | */ |
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538 | uint32_t QSPID_ReadWriteQSPI(QspiDma_t *pQspidma, Access_t const ReadWrite) |
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539 | { |
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540 | QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer; |
---|
541 | uint8_t chanNum; |
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542 | uint32_t semTimer = 0x7FF; |
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543 | |
---|
544 | //assert(pBuffer->pDataTx); |
---|
545 | |
---|
546 | if (pQspidma->progress) |
---|
547 | return QSPID_ERROR_LOCK; |
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548 | |
---|
549 | LockMutex(pQspidma->progress, semTimer); |
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550 | |
---|
551 | if (QSPID_configureQpsiDma |
---|
552 | (pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite)) |
---|
553 | return QSPID_ERROR_LOCK; |
---|
554 | |
---|
555 | if (ReadWrite == WriteAccess) { |
---|
556 | chanNum = pQspidma->TxChNum; |
---|
557 | SCB_CleanDCache_by_Addr((uint32_t *)pBuffer->pDataTx, pBuffer->TxDataSize); |
---|
558 | } else if (ReadWrite == ReadAccess) |
---|
559 | chanNum = pQspidma->RxChNum; |
---|
560 | else |
---|
561 | TRACE_ERROR("%s QSPI Access Error\n\r", __FUNCTION__); |
---|
562 | |
---|
563 | /* Start DMA 0(RX) && 1(TX) */ |
---|
564 | if (XDMAD_StartTransfer(pQspidma->pXdmad, chanNum)) |
---|
565 | return QSPID_ERROR_LOCK; |
---|
566 | |
---|
567 | return 0; |
---|
568 | } |
---|
569 | |
---|
570 | /** |
---|
571 | * \brief Starts a SPI master transfer. This is a non blocking function. It will |
---|
572 | * return as soon as the transfer is started. |
---|
573 | * |
---|
574 | * \param pSpid Pointer to a Spid instance. |
---|
575 | * \param pCommand Pointer to the SPI command to execute. |
---|
576 | * \returns 0 if the transfer has been started successfully; otherwise returns |
---|
577 | * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not |
---|
578 | * valid. |
---|
579 | */ |
---|
580 | uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite) |
---|
581 | { |
---|
582 | QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer; |
---|
583 | uint32_t semTimer = 0x7FF; |
---|
584 | |
---|
585 | assert(pBuffer->pDataRx); |
---|
586 | assert(pBuffer->pDataTx); |
---|
587 | |
---|
588 | /* Try to get the dataflash semaphore */ |
---|
589 | if (pQspidma->progress) |
---|
590 | |
---|
591 | return QSPID_ERROR_LOCK; |
---|
592 | |
---|
593 | LockMutex(pQspidma->progress, semTimer); |
---|
594 | |
---|
595 | if (QSPID_configureQpsiDma |
---|
596 | (pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite)) |
---|
597 | return QSPID_ERROR_LOCK; |
---|
598 | |
---|
599 | SCB_CleanDCache_by_Addr((uint32_t *)pBuffer->pDataTx, pBuffer->TxDataSize); |
---|
600 | |
---|
601 | /* Start DMA 0(RX) && 1(TX) */ |
---|
602 | if (XDMAD_StartTransfer(pQspidma->pXdmad, pQspidma->RxChNum)) |
---|
603 | return QSPID_ERROR_LOCK; |
---|
604 | |
---|
605 | if (XDMAD_StartTransfer(pQspidma->pXdmad, pQspidma->TxChNum)) |
---|
606 | return QSPID_ERROR_LOCK; |
---|
607 | |
---|
608 | return 0; |
---|
609 | } |
---|
610 | |
---|
611 | /** |
---|
612 | * \brief Check if the QSPI driver is busy. |
---|
613 | * |
---|
614 | * \param pSpid Pointer to a Spid instance. |
---|
615 | * \returns 1 if the SPI driver is currently busy executing a command; otherwise |
---|
616 | */ |
---|
617 | uint32_t QSPID_IsBusy(volatile uint8_t *QspiSemaphore) |
---|
618 | { |
---|
619 | if (Is_LockFree(QspiSemaphore)) |
---|
620 | return 1; |
---|
621 | else |
---|
622 | return 0; |
---|
623 | } |
---|