1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /** \file */ |
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31 | |
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32 | /** \addtogroup dmac_module Working with DMAC |
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33 | * \ingroup peripherals_module |
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34 | * |
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35 | * \section Usage |
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36 | * <ul> |
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37 | * <li> Enable or disable the a DMAC controller with DMAC_Enable() and or |
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38 | * DMAC_Disable().</li> |
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39 | * <li> Enable or disable %Dma interrupt using DMAC_EnableIt()or |
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40 | * DMAC_DisableIt().</li> |
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41 | * <li> Get %Dma interrupt status by DMAC_GetStatus() and |
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42 | * DMAC_GetInterruptMask().</li> |
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43 | * <li> Enable or disable specified %Dma channel with DMAC_EnableChannel() or |
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44 | * DMAC_DisableChannel().</li> |
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45 | * <li> Get %Dma channel status by DMAC_GetChannelStatus().</li> |
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46 | * <li> ControlA and ControlB register is set by DMAC_SetControlA() and |
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47 | * DMAC_SetControlB().</li> |
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48 | * <li> Configure source and/or destination start address with |
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49 | * DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().</li> |
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50 | * <li> Set %Dma descriptor address using DMAC_SetDescriptorAddr().</li> |
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51 | * <li> Set source transfer buffer size with DMAC_SetBufferSize().</li> |
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52 | * <li> Configure source and/or destination Picture-In-Picuture mode with |
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53 | * DMAC_SetSourcePip() and/or DMAC_SetDestPip().</li> |
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54 | * </ul> |
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55 | * |
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56 | * For more accurate information, please look at the DMAC section of the |
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57 | * Datasheet. |
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58 | * |
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59 | * \sa \ref dmad_module |
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60 | * |
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61 | * Related files :\n |
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62 | * \ref dmac.c\n |
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63 | * \ref dmac.h.\n |
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64 | * |
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65 | */ |
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66 | |
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67 | #ifndef DMAC_H |
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68 | #define DMAC_H |
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69 | /**@{*/ |
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70 | |
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71 | /*------------------------------------------------------------------------------ |
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72 | * Headers |
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73 | *----------------------------------------------------------------------------*/ |
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74 | |
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75 | #include "chip.h" |
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76 | |
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77 | #ifndef __rtems__ |
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78 | #include <../../../../utils/utility.h> |
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79 | #endif /* __rtems__ */ |
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80 | #include <stdint.h> |
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81 | #include <assert.h> |
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82 | |
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83 | /*------------------------------------------------------------------------------ |
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84 | * Definitions |
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85 | *----------------------------------------------------------------------------*/ |
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86 | |
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87 | /** \addtogroup dmac_defines DMAC Definitions |
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88 | * @{ |
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89 | */ |
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90 | /** Number of DMA channels */ |
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91 | #define XDMAC_CONTROLLER_NUM 1 |
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92 | /** Number of DMA channels */ |
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93 | #define XDMAC_CHANNEL_NUM 24 |
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94 | /** Max DMA single transfer size */ |
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95 | #define XDMAC_MAX_BT_SIZE 0xFFFF |
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96 | /** @}*/ |
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97 | |
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98 | /*---------------------------------------------------------------------------- |
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99 | * Macro |
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100 | *----------------------------------------------------------------------------*/ |
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101 | #define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ |
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102 | ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ |
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103 | (XDMAC_CC_DWIDTH_WORD))) |
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104 | #define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ |
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105 | ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ |
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106 | ((s==2)? XDMAC_CC_SAM_UBS_AM : \ |
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107 | XDMAC_CC_SAM_UBS_DS_AM))) |
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108 | #define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ |
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109 | ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ |
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110 | ((d==2)? XDMAC_CC_DAM_UBS_AM : \ |
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111 | XDMAC_CC_DAM_UBS_DS_AM))) |
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112 | #define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ |
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113 | XDMAC_CC_MEMSET_HW_MODE) |
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114 | |
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115 | /*------------------------------------------------------------------------------ |
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116 | * Global functions |
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117 | *----------------------------------------------------------------------------*/ |
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118 | /** \addtogroup dmac_functions |
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119 | * @{ |
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120 | */ |
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121 | |
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122 | #ifdef __cplusplus |
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123 | extern "C" { |
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124 | #endif |
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125 | |
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126 | /** |
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127 | * \brief Get XDMAC global type. |
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128 | * |
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129 | * \param pXdmac Pointer to the XDMAC peripheral. |
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130 | */ |
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131 | static inline uint32_t XDMAC_GetType(Xdmac *pXdmac) |
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132 | { |
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133 | assert(pXdmac); |
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134 | return pXdmac->XDMAC_GTYPE; |
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135 | } |
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136 | |
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137 | /** |
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138 | * \brief Get XDMAC global configuration. |
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139 | * |
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140 | * \param pXdmac Pointer to the XDMAC peripheral. |
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141 | */ |
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142 | static inline uint32_t XDMAC_GetConfig(Xdmac *pXdmac) |
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143 | { |
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144 | assert(pXdmac); |
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145 | return pXdmac->XDMAC_GCFG; |
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146 | } |
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147 | |
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148 | /** |
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149 | * \brief Get XDMAC global weighted arbiter configuration. |
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150 | * |
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151 | * \param pXdmac Pointer to the XDMAC peripheral. |
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152 | */ |
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153 | static inline uint32_t XDMAC_GetArbiter(Xdmac *pXdmac) |
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154 | { |
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155 | assert(pXdmac); |
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156 | return pXdmac->XDMAC_GWAC; |
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157 | } |
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158 | |
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159 | /** |
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160 | * \brief Enables XDMAC global interrupt. |
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161 | * |
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162 | * \param pXdmac Pointer to the XDMAC peripheral. |
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163 | * \param dwInteruptMask IT to be enabled. |
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164 | */ |
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165 | static inline void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) |
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166 | { |
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167 | assert(pXdmac); |
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168 | pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << dwInteruptMask); |
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169 | } |
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170 | |
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171 | /** |
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172 | * \brief Disables XDMAC global interrupt |
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173 | * |
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174 | * \param pXdmac Pointer to the XDMAC peripheral. |
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175 | * \param dwInteruptMask IT to be enabled |
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176 | */ |
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177 | static inline void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask) |
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178 | { |
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179 | assert(pXdmac); |
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180 | pXdmac->XDMAC_GID = (XDMAC_GID_ID0 << dwInteruptMask); |
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181 | } |
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182 | |
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183 | /** |
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184 | * \brief Get XDMAC global interrupt mask. |
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185 | * |
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186 | * \param pXdmac Pointer to the XDMAC peripheral. |
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187 | */ |
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188 | static inline uint32_t XDMAC_GetGItMask(Xdmac *pXdmac) |
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189 | { |
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190 | assert(pXdmac); |
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191 | return (pXdmac->XDMAC_GIM); |
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192 | } |
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193 | |
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194 | /** |
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195 | * \brief Get XDMAC global interrupt status. |
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196 | * |
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197 | * \param pXdmac Pointer to the XDMAC peripheral. |
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198 | */ |
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199 | static inline uint32_t XDMAC_GetGIsr(Xdmac *pXdmac) |
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200 | { |
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201 | assert(pXdmac); |
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202 | return (pXdmac->XDMAC_GIS); |
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203 | } |
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204 | |
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205 | /** |
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206 | * \brief Get XDMAC masked global interrupt. |
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207 | * |
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208 | * \param pXdmac Pointer to the XDMAC peripheral. |
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209 | */ |
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210 | static inline uint32_t XDMAC_GetMaskedGIsr(Xdmac *pXdmac) |
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211 | { |
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212 | uint32_t _dwStatus; |
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213 | assert(pXdmac); |
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214 | _dwStatus = pXdmac->XDMAC_GIS; |
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215 | _dwStatus &= pXdmac->XDMAC_GIM; |
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216 | return _dwStatus; |
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217 | } |
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218 | |
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219 | /** |
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220 | * \brief enables the relevant channel of given XDMAC. |
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221 | * |
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222 | * \param pXdmac Pointer to the XDMAC peripheral. |
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223 | * \param channel Particular channel number. |
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224 | */ |
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225 | static inline void XDMAC_EnableChannel(Xdmac *pXdmac, uint8_t channel) |
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226 | { |
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227 | assert(pXdmac); |
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228 | assert(channel < XDMAC_CHANNEL_NUM); |
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229 | pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); |
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230 | } |
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231 | |
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232 | /** |
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233 | * \brief enables the relevant channels of given XDMAC. |
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234 | * |
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235 | * \param pXdmac Pointer to the XDMAC peripheral. |
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236 | * \param bmChannels Channels bitmap. |
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237 | */ |
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238 | static inline void XDMAC_EnableChannels(Xdmac *pXdmac, uint32_t bmChannels) |
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239 | { |
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240 | assert(pXdmac); |
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241 | pXdmac->XDMAC_GE = bmChannels; |
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242 | } |
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243 | |
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244 | /** |
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245 | * \brief Disables the relevant channel of given XDMAC. |
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246 | * |
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247 | * \param pXdmac Pointer to the XDMAC peripheral. |
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248 | * \param channel Particular channel number. |
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249 | */ |
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250 | static inline void XDMAC_DisableChannel(Xdmac *pXdmac, uint8_t channel) |
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251 | { |
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252 | assert(pXdmac); |
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253 | assert(channel < XDMAC_CHANNEL_NUM); |
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254 | pXdmac->XDMAC_GD = (XDMAC_GD_DI0 << channel); |
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255 | } |
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256 | |
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257 | /** |
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258 | * \brief Disables the relevant channels of given XDMAC. |
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259 | * |
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260 | * \param pXdmac Pointer to the XDMAC peripheral. |
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261 | * \param bmChannels Channels bitmap. |
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262 | */ |
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263 | static inline void XDMAC_DisableChannels(Xdmac *pXdmac, uint32_t bmChannels) |
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264 | { |
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265 | assert(pXdmac); |
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266 | pXdmac->XDMAC_GD = bmChannels; |
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267 | } |
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268 | |
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269 | |
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270 | /** |
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271 | * \brief Get Global channel status of given XDMAC. |
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272 | * \note: When set to 1, this bit indicates that the channel x is enabled. |
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273 | If a channel disable request is issued, this bit remains asserted |
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274 | until pending transaction is completed. |
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275 | * \param pXdmac Pointer to the XDMAC peripheral. |
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276 | */ |
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277 | static inline uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac) |
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278 | { |
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279 | assert(pXdmac); |
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280 | return pXdmac->XDMAC_GS; |
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281 | } |
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282 | |
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283 | /** |
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284 | * \brief Suspend the relevant channel's read. |
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285 | * |
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286 | * \param pXdmac Pointer to the XDMAC peripheral. |
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287 | * \param channel Particular channel number. |
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288 | */ |
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289 | static inline void XDMAC_SuspendReadChannel(Xdmac *pXdmac, uint8_t channel) |
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290 | { |
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291 | assert(pXdmac); |
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292 | assert(channel < XDMAC_CHANNEL_NUM); |
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293 | pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel; |
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294 | } |
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295 | |
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296 | /** |
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297 | * \brief Suspend the relevant channel's write. |
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298 | * |
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299 | * \param pXdmac Pointer to the XDMAC peripheral. |
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300 | * \param channel Particular channel number. |
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301 | */ |
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302 | static inline void XDMAC_SuspendWriteChannel(Xdmac *pXdmac, uint8_t channel) |
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303 | { |
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304 | assert(pXdmac); |
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305 | assert(channel < XDMAC_CHANNEL_NUM); |
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306 | pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel; |
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307 | } |
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308 | |
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309 | /** |
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310 | * \brief Suspend the relevant channel's read & write. |
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311 | * |
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312 | * \param pXdmac Pointer to the XDMAC peripheral. |
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313 | * \param channel Particular channel number. |
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314 | */ |
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315 | static inline void XDMAC_SuspendReadWriteChannel(Xdmac *pXdmac, uint8_t channel) |
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316 | { |
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317 | assert(pXdmac); |
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318 | assert(channel < XDMAC_CHANNEL_NUM); |
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319 | pXdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel); |
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320 | } |
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321 | |
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322 | /** |
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323 | * \brief Resume the relevant channel's read & write. |
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324 | * |
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325 | * \param pXdmac Pointer to the XDMAC peripheral. |
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326 | * \param channel Particular channel number. |
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327 | */ |
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328 | static inline void XDMAC_ResumeReadWriteChannel(Xdmac *pXdmac, uint8_t channel) |
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329 | { |
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330 | assert(pXdmac); |
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331 | assert(channel < XDMAC_CHANNEL_NUM); |
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332 | pXdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel); |
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333 | } |
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334 | |
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335 | /** |
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336 | * \brief Set software transfer request on the relevant channel. |
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337 | * |
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338 | * \param pXdmac Pointer to the XDMAC peripheral. |
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339 | * \param channel Particular channel number. |
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340 | */ |
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341 | static inline void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel) |
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342 | { |
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343 | |
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344 | assert(pXdmac); |
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345 | assert(channel < XDMAC_CHANNEL_NUM); |
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346 | pXdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel); |
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347 | } |
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348 | |
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349 | /** |
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350 | * \brief Get software transfer status of the relevant channel. |
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351 | * |
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352 | * \param pXdmac Pointer to the XDMAC peripheral. |
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353 | */ |
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354 | static inline uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac) |
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355 | { |
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356 | |
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357 | assert(pXdmac); |
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358 | return pXdmac->XDMAC_GSWS; |
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359 | } |
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360 | |
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361 | /** |
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362 | * \brief Get interrupt status for the relevant channel of given XDMA. |
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363 | * |
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364 | * \param pXdmac Pointer to the XDMAC peripheral. |
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365 | * \param channel Particular channel number. |
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366 | */ |
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367 | static inline uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel) |
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368 | { |
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369 | assert(pXdmac); |
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370 | assert(channel < XDMAC_CHANNEL_NUM); |
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371 | return pXdmac->XDMAC_CHID[channel].XDMAC_CIS; |
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372 | } |
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373 | |
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374 | /** |
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375 | * \brief Set software flush request on the relevant channel. |
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376 | * \note: This API is used as polling without enabling FIE interrupt. |
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377 | * The user can use it in interrupt mode after deleting while sentense. |
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378 | * \param pXdmac Pointer to the XDMAC peripheral. |
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379 | * \param channel Particular channel number. |
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380 | */ |
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381 | static inline void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel) |
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382 | { |
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383 | assert(pXdmac); |
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384 | assert(channel < XDMAC_CHANNEL_NUM); |
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385 | pXdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel); |
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386 | |
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387 | while (!(XDMAC_GetChannelIsr(pXdmac, channel) & XDMAC_CIS_FIS)); |
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388 | } |
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389 | |
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390 | /** |
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391 | * \brief Disable interrupt with mask on the relevant channel of given XDMA. |
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392 | * |
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393 | * \param pXdmac Pointer to the XDMAC peripheral. |
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394 | * \param channel Particular channel number. |
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395 | * \param dwInteruptMask Interrupt mask. |
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396 | */ |
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397 | static inline void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, |
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398 | uint8_t dwInteruptMask) |
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399 | { |
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400 | assert(pXdmac); |
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401 | assert(channel < XDMAC_CHANNEL_NUM); |
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402 | pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask; |
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403 | } |
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404 | |
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405 | /** |
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406 | * \brief Enable interrupt with mask on the relevant channel of given XDMA. |
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407 | * |
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408 | * \param pXdmac Pointer to the XDMAC peripheral. |
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409 | * \param channel Particular channel number. |
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410 | * \param dwInteruptMask Interrupt mask. |
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411 | */ |
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412 | static inline void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, |
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413 | uint8_t dwInteruptMask) |
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414 | { |
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415 | assert(pXdmac); |
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416 | assert(channel < XDMAC_CHANNEL_NUM); |
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417 | pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask; |
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418 | } |
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419 | |
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420 | /** |
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421 | * \brief Get interrupt mask for the relevant channel of given XDMA. |
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422 | * |
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423 | * \param pXdmac Pointer to the XDMAC peripheral. |
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424 | * \param channel Particular channel number. |
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425 | */ |
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426 | static inline uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel) |
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427 | { |
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428 | assert(pXdmac); |
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429 | assert(channel < XDMAC_CHANNEL_NUM); |
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430 | return pXdmac->XDMAC_CHID[channel].XDMAC_CIM; |
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431 | } |
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432 | |
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433 | /** |
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434 | * \brief Get masked interrupt status for the relevant channel of given XDMA. |
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435 | * |
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436 | * \param pXdmac Pointer to the XDMAC peripheral. |
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437 | * \param channel Particular channel number. |
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438 | */ |
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439 | static inline uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel) |
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440 | { |
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441 | uint32_t status; |
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442 | assert(pXdmac); |
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443 | assert(channel < XDMAC_CHANNEL_NUM); |
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444 | status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS; |
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445 | status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM; |
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446 | |
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447 | return status; |
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448 | } |
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449 | |
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450 | /** |
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451 | * \brief Set source address for the relevant channel of given XDMA. |
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452 | * |
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453 | * \param pXdmac Pointer to the XDMAC peripheral. |
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454 | * \param channel Particular channel number. |
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455 | * \param addr Source address. |
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456 | */ |
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457 | static inline void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) |
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458 | { |
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459 | assert(pXdmac); |
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460 | assert(channel < XDMAC_CHANNEL_NUM); |
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461 | pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr; |
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462 | } |
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463 | |
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464 | /** |
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465 | * \brief Set destination address for the relevant channel of given XDMA. |
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466 | * |
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467 | * \param pXdmac Pointer to the XDMAC peripheral. |
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468 | * \param channel Particular channel number. |
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469 | * \param addr Destination address. |
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470 | */ |
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471 | static inline void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) |
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472 | { |
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473 | assert(pXdmac); |
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474 | assert(channel < XDMAC_CHANNEL_NUM); |
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475 | pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr; |
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476 | } |
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477 | |
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478 | /** |
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479 | * \brief Set next descriptor's address & interface for the relevant channel of |
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480 | * given XDMA. |
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481 | * |
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482 | * \param pXdmac Pointer to the XDMAC peripheral. |
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483 | * \param channel Particular channel number. |
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484 | * \param addr Address of next descriptor. |
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485 | * \param ndaif Interface of next descriptor. |
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486 | */ |
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487 | static inline void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, |
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488 | uint32_t addr, uint8_t ndaif) |
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489 | { |
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490 | assert(pXdmac); |
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491 | assert(ndaif < 2); |
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492 | assert(channel < XDMAC_CHANNEL_NUM); |
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493 | pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = (addr & 0xFFFFFFFC) | ndaif; |
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494 | } |
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495 | |
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496 | /** |
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497 | * \brief Set next descriptor's configuration for the relevant channel of |
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498 | * given XDMA. |
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499 | * |
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500 | * \param pXdmac Pointer to the XDMAC peripheral. |
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501 | * \param channel Particular channel number. |
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502 | * \param config Configuration of next descriptor. |
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503 | */ |
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504 | static inline void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint8_t config) |
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505 | { |
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506 | assert(pXdmac); |
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507 | assert(channel < XDMAC_CHANNEL_NUM); |
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508 | pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config; |
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509 | } |
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510 | |
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511 | /** |
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512 | * \brief Set microblock length for the relevant channel of given XDMA. |
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513 | * |
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514 | * \param pXdmac Pointer to the XDMAC peripheral. |
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515 | * \param channel Particular channel number. |
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516 | * \param ublen Microblock length. |
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517 | */ |
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518 | static inline void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen) |
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519 | { |
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520 | assert(pXdmac); |
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521 | assert(channel < XDMAC_CHANNEL_NUM); |
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522 | pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen); |
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523 | } |
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524 | |
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525 | /** |
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526 | * \brief Set block length for the relevant channel of given XDMA. |
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527 | * |
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528 | * \param pXdmac Pointer to the XDMAC peripheral. |
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529 | * \param channel Particular channel number. |
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530 | * \param blen Block length. |
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531 | */ |
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532 | static inline void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint16_t blen) |
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533 | { |
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534 | assert(pXdmac); |
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535 | assert(channel < XDMAC_CHANNEL_NUM); |
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536 | pXdmac->XDMAC_CHID[channel].XDMAC_CBC = XDMAC_CBC_BLEN(blen); |
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537 | } |
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538 | |
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539 | /** |
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540 | * \brief Set configuration for the relevant channel of given XDMA. |
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541 | * |
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542 | * \param pXdmac Pointer to the XDMAC peripheral. |
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543 | * \param channel Particular channel number. |
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544 | * \param config Channel configuration. |
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545 | */ |
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546 | static inline void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config) |
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547 | { |
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548 | assert(pXdmac); |
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549 | assert(channel < XDMAC_CHANNEL_NUM); |
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550 | pXdmac->XDMAC_CHID[channel].XDMAC_CC = config; |
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551 | } |
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552 | |
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553 | /** |
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554 | * \brief Get the relevant channel's configuration of given XDMA. |
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555 | * |
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556 | * \param pXdmac Pointer to the XDMAC peripheral. |
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557 | * \param channel Particular channel number. |
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558 | */ |
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559 | static inline uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel) |
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560 | { |
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561 | assert(pXdmac); |
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562 | assert(channel < XDMAC_CHANNEL_NUM); |
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563 | return pXdmac->XDMAC_CHID[channel].XDMAC_CC; |
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564 | } |
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565 | |
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566 | /** |
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567 | * \brief Set the relevant channel's data stride memory pattern of given XDMA. |
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568 | * |
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569 | * \param pXdmac Pointer to the XDMAC peripheral. |
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570 | * \param channel Particular channel number. |
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571 | * \param dds_msp Data stride memory pattern. |
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572 | */ |
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573 | static inline void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, |
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574 | uint32_t dds_msp) |
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575 | { |
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576 | |
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577 | assert(pXdmac); |
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578 | assert(channel < XDMAC_CHANNEL_NUM); |
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579 | pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp; |
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580 | } |
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581 | |
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582 | /** |
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583 | * \brief Set the relevant channel's source microblock stride of given XDMA. |
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584 | * |
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585 | * \param pXdmac Pointer to the XDMAC peripheral. |
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586 | * \param channel Particular channel number. |
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587 | * \param subs Source microblock stride. |
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588 | */ |
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589 | static inline void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, |
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590 | uint32_t subs) |
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591 | { |
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592 | assert(pXdmac); |
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593 | assert(channel < XDMAC_CHANNEL_NUM); |
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594 | pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs); |
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595 | } |
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596 | |
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597 | /** |
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598 | * \brief Set the relevant channel's destination microblock stride of given XDMA. |
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599 | * |
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600 | * \param pXdmac Pointer to the XDMAC peripheral. |
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601 | * \param channel Particular channel number. |
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602 | * \param dubs Destination microblock stride. |
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603 | */ |
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604 | static inline void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, |
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605 | uint32_t dubs) |
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606 | { |
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607 | assert(pXdmac); |
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608 | assert(channel < XDMAC_CHANNEL_NUM); |
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609 | pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs); |
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610 | } |
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611 | |
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612 | /** |
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613 | * \brief Get the relevant channel's destination address of given XDMA. |
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614 | * |
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615 | * \param pXdmac Pointer to the XDMAC peripheral. |
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616 | * \param channel Particular channel number. |
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617 | */ |
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618 | static inline uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel) |
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619 | { |
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620 | assert(pXdmac); |
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621 | assert(channel < XDMAC_CHANNEL_NUM); |
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622 | return pXdmac->XDMAC_CHID[channel].XDMAC_CDA; |
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623 | } |
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624 | |
---|
625 | static inline void XDMAC_StartTransfer(Xdmac *pXdmac, uint8_t channel) |
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626 | { |
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627 | assert(pXdmac); |
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628 | assert(channel < XDMAC_CHANNEL_NUM); |
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629 | pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); |
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630 | pXdmac->XDMAC_GIE = (XDMAC_GIE_IE0 << channel); |
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631 | } |
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632 | |
---|
633 | #ifdef __cplusplus |
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634 | } |
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635 | #endif |
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636 | |
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637 | /** @}*/ |
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638 | /**@}*/ |
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639 | #endif //#ifndef DMAC_H |
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640 | |
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