source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/samv71/samv71q21.h @ e1eeb883

5
Last change on this file since e1eeb883 was e1eeb883, checked in by Sebastian Huber <sebastian.huber@…>, on 01/12/16 at 14:34:31

bsp/atsam: Import SAM Software Package

Import selected files of the "SAM V71 / V70 / E70 / S70 Software
Package" obtained from the "SAMV71-XULT GNU Software Package 1.5".

Converted files via dos2unix before import.

Update #2529.
  • Property mode set to 100644
File size: 35.2 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71Q21_
31#define _SAMV71Q21_
32
33/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions
34  This file defines all structures and symbols for SAMV71Q21:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAMV71Q21 */
52/* ************************************************************************** */
53/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAMV71Q21 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAMV71Q21 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAMV71Q21 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAMV71Q21 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAMV71Q21 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAMV71Q21 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAMV71Q21 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAMV71Q21 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAMV71Q21 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */
82  PIOC_IRQn            = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */
83  USART0_IRQn          = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */
84  USART1_IRQn          = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */
85  USART2_IRQn          = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */
86  PIOD_IRQn            = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */
87  PIOE_IRQn            = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */
88  HSMCI_IRQn           = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */
89  TWIHS0_IRQn          = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWIHS0) */
90  TWIHS1_IRQn          = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWIHS1) */
91  SPI0_IRQn            = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */
92  SSC_IRQn             = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */
93  TC0_IRQn             = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */
94  TC1_IRQn             = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */
95  TC2_IRQn             = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */
96  TC3_IRQn             = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */
97  TC4_IRQn             = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */
98  TC5_IRQn             = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */
99  AFEC0_IRQn           = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */
100  DACC_IRQn            = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */
101  PWM0_IRQn            = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */
102  ICM_IRQn             = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */
103  ACC_IRQn             = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */
104  USBHS_IRQn           = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */
105  MCAN0_IRQn           = 35, /**< 35 SAMV71Q21 MCAN Controller 0 (MCAN0) */
106  MCAN0_LINE1_IRQn     = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */
107  MCAN1_IRQn           = 37, /**< 37 SAMV71Q21 MCAN Controller 1 (MCAN1) */
108  MCAN1_LINE1_IRQn     = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */
109  GMAC_IRQn            = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */
110  AFEC1_IRQn           = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */
111  TWIHS2_IRQn          = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWIHS2) */
112  SPI1_IRQn            = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */
113  QSPI_IRQn            = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */
114  UART2_IRQn           = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */
115  UART3_IRQn           = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */
116  UART4_IRQn           = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */
117  TC6_IRQn             = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */
118  TC7_IRQn             = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */
119  TC8_IRQn             = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */
120  TC9_IRQn             = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */
121  TC10_IRQn            = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */
122  TC11_IRQn            = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */
123  MLB_IRQn             = 53, /**< 53 SAMV71Q21 MediaLB (MLB) */
124  AES_IRQn             = 56, /**< 56 SAMV71Q21 AES (AES) */
125  TRNG_IRQn            = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */
126  XDMAC_IRQn           = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */
127  ISI_IRQn             = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */
128  PWM1_IRQn            = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */
129  SDRAMC_IRQn          = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */
130  RSWDT_IRQn           = 63, /**< 63 SAMV71Q21 Reinforced Secure Watchdog Timer (RSWDT) */
131
132  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
133} IRQn_Type;
134
135typedef struct _DeviceVectors
136{
137  /* Stack pointer */
138  void* pvStack;
139
140  /* Cortex-M handlers */
141  void* pfnReset_Handler;
142  void* pfnNMI_Handler;
143  void* pfnHardFault_Handler;
144  void* pfnMemManage_Handler;
145  void* pfnBusFault_Handler;
146  void* pfnUsageFault_Handler;
147  void* pfnReserved1_Handler;
148  void* pfnReserved2_Handler;
149  void* pfnReserved3_Handler;
150  void* pfnReserved4_Handler;
151  void* pfnSVC_Handler;
152  void* pfnDebugMon_Handler;
153  void* pfnReserved5_Handler;
154  void* pfnPendSV_Handler;
155  void* pfnSysTick_Handler;
156
157  /* Peripheral handlers */
158  void* pfnSUPC_Handler;   /*  0 Supply Controller */
159  void* pfnRSTC_Handler;   /*  1 Reset Controller */
160  void* pfnRTC_Handler;    /*  2 Real Time Clock */
161  void* pfnRTT_Handler;    /*  3 Real Time Timer */
162  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
163  void* pfnPMC_Handler;    /*  5 Power Management Controller */
164  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
165  void* pfnUART0_Handler;  /*  7 UART 0 */
166  void* pfnUART1_Handler;  /*  8 UART 1 */
167  void* pvReserved9;
168  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
169  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
170  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
171  void* pfnUSART0_Handler; /* 13 USART 0 */
172  void* pfnUSART1_Handler; /* 14 USART 1 */
173  void* pfnUSART2_Handler; /* 15 USART 2 */
174  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
175  void* pfnPIOE_Handler;   /* 17 Parallel I/O Controller E */
176  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
177  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
178  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
179  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
180  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
181  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
182  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
183  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
184  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
185  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
186  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
187  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
188  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
189  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
190  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
191  void* pfnACC_Handler;    /* 33 Analog Comparator */
192  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
193  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
194  void* pfnMCAN0_Line1_Handler;  /* 36 MCAN Controller 0 */
195  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
196  void* pfnMCAN1_Line1_Handler;  /* 38 MCAN Controller 1 */
197  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
198  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
199  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
200  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
201  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
202  void* pfnUART2_Handler;  /* 44 UART 2 */
203  void* pfnUART3_Handler;  /* 45 UART 3 */
204  void* pfnUART4_Handler;  /* 46 UART 4 */
205  void* pfnTC6_Handler;    /* 47 Timer/Counter 6 */
206  void* pfnTC7_Handler;    /* 48 Timer/Counter 7 */
207  void* pfnTC8_Handler;    /* 49 Timer/Counter 8 */
208  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
209  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
210  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
211  void* pfnMLB_Handler;    /* 53 MediaLB */
212  void* pvReserved54;
213  void* pvReserved55;
214  void* pfnAES_Handler;    /* 56 AES */
215  void* pfnTRNG_Handler;   /* 57 True Random Generator */
216  void* pfnXDMAC_Handler;  /* 58 DMA */
217  void* pfnISI_Handler;    /* 59 Camera Interface */
218  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
219  void* pvReserved61;
220  void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
221  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
222} DeviceVectors;
223
224/* Cortex-M7 core handlers */
225void Reset_Handler      ( void );
226void NMI_Handler        ( void );
227void HardFault_Handler  ( void );
228void MemManage_Handler  ( void );
229void BusFault_Handler   ( void );
230void UsageFault_Handler ( void );
231void SVC_Handler        ( void );
232void DebugMon_Handler   ( void );
233void PendSV_Handler     ( void );
234void SysTick_Handler    ( void );
235
236/* Peripherals handlers */
237void ACC_Handler        ( void );
238void AES_Handler        ( void );
239void AFEC0_Handler      ( void );
240void AFEC1_Handler      ( void );
241void DACC_Handler       ( void );
242void EFC_Handler        ( void );
243void GMAC_Handler       ( void );
244void HSMCI_Handler      ( void );
245void ICM_Handler        ( void );
246void ISI_Handler        ( void );
247void MCAN0_Handler      ( void );
248void MCAN0_Line1_Handler  ( void );
249void MCAN1_Handler      ( void );
250void MCAN1_Line1_Handler  ( void );
251void MLB_Handler        ( void );
252void PIOA_Handler       ( void );
253void PIOB_Handler       ( void );
254void PIOC_Handler       ( void );
255void PIOD_Handler       ( void );
256void PIOE_Handler       ( void );
257void PMC_Handler        ( void );
258void PWM0_Handler       ( void );
259void PWM1_Handler       ( void );
260void QSPI_Handler       ( void );
261void RSTC_Handler       ( void );
262void RSWDT_Handler      ( void );
263void RTC_Handler        ( void );
264void RTT_Handler        ( void );
265void SDRAMC_Handler     ( void );
266void SPI0_Handler       ( void );
267void SPI1_Handler       ( void );
268void SSC_Handler        ( void );
269void SUPC_Handler       ( void );
270void TC0_Handler        ( void );
271void TC1_Handler        ( void );
272void TC2_Handler        ( void );
273void TC3_Handler        ( void );
274void TC4_Handler        ( void );
275void TC5_Handler        ( void );
276void TC6_Handler        ( void );
277void TC7_Handler        ( void );
278void TC8_Handler        ( void );
279void TC9_Handler        ( void );
280void TC10_Handler       ( void );
281void TC11_Handler       ( void );
282void TRNG_Handler       ( void );
283void TWIHS0_Handler     ( void );
284void TWIHS1_Handler     ( void );
285void TWIHS2_Handler     ( void );
286void UART0_Handler      ( void );
287void UART1_Handler      ( void );
288void UART2_Handler      ( void );
289void UART3_Handler      ( void );
290void UART4_Handler      ( void );
291void USART0_Handler     ( void );
292void USART1_Handler     ( void );
293void USART2_Handler     ( void );
294void USBHS_Handler      ( void );
295void WDT_Handler        ( void );
296void XDMAC_Handler      ( void );
297
298/**
299 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
300 */
301
302#define __CM7_REV              0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */
303#define __MPU_PRESENT          1      /**< SAMV71Q21 does provide a MPU */
304#define __NVIC_PRIO_BITS       3      /**< SAMV71Q21 uses 3 Bits for the Priority Levels */
305#define __FPU_PRESENT          1      /**< SAMV71Q21 does provide a FPU                */
306#define __FPU_DP               1      /**< SAMV71Q21 Double precision FPU              */
307#define __ICACHE_PRESENT       1      /**< SAMV71Q21 does provide an Instruction Cache */
308#define __DCACHE_PRESENT       1      /**< SAMV71Q21 does provide a Data Cache         */
309#define __DTCM_PRESENT         1      /**< SAMV71Q21 does provide a Data TCM           */
310#define __ITCM_PRESENT         1      /**< SAMV71Q21 does provide an Instruction TCM   */
311#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
312
313/*
314 * \brief CMSIS includes
315 */
316
317#include <core_cm7.h>
318#if !defined DONT_USE_CMSIS_INIT
319#include "system_samv71.h"
320#endif /* DONT_USE_CMSIS_INIT */
321
322/*@}*/
323
324/* ************************************************************************** */
325/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */
326/* ************************************************************************** */
327/** \addtogroup SAMV71Q21_api Peripheral Software API */
328/*@{*/
329
330#include "component/component_acc.h"
331#include "component/component_aes.h"
332#include "component/component_afec.h"
333#include "component/component_chipid.h"
334#include "component/component_dacc.h"
335#include "component/component_efc.h"
336#include "component/component_gmac.h"
337#include "component/component_gpbr.h"
338#include "component/component_hsmci.h"
339#include "component/component_icm.h"
340#include "component/component_isi.h"
341#include "component/component_matrix.h"
342#include "component/component_mcan.h"
343#include "component/component_mlb.h"
344#include "component/component_pio.h"
345#include "component/component_pmc.h"
346#include "component/component_pwm.h"
347#include "component/component_qspi.h"
348#include "component/component_rstc.h"
349#include "component/component_rswdt.h"
350#include "component/component_rtc.h"
351#include "component/component_rtt.h"
352#include "component/component_sdramc.h"
353#include "component/component_smc.h"
354#include "component/component_spi.h"
355#include "component/component_ssc.h"
356#include "component/component_supc.h"
357#include "component/component_tc.h"
358#include "component/component_trng.h"
359#include "component/component_twihs.h"
360#include "component/component_uart.h"
361#include "component/component_usart.h"
362#include "component/component_usbhs.h"
363#include "component/component_utmi.h"
364#include "component/component_wdt.h"
365#include "component/component_xdmac.h"
366/*@}*/
367
368/* ************************************************************************** */
369/*   REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */
370/* ************************************************************************** */
371/** \addtogroup SAMV71Q21_reg Registers Access Definitions */
372/*@{*/
373
374#include "instance/instance_hsmci.h"
375#include "instance/instance_ssc.h"
376#include "instance/instance_spi0.h"
377#include "instance/instance_tc0.h"
378#include "instance/instance_tc1.h"
379#include "instance/instance_tc2.h"
380#include "instance/instance_twihs0.h"
381#include "instance/instance_twihs1.h"
382#include "instance/instance_pwm0.h"
383#include "instance/instance_usart0.h"
384#include "instance/instance_usart1.h"
385#include "instance/instance_usart2.h"
386#include "instance/instance_mcan0.h"
387#include "instance/instance_mcan1.h"
388#include "instance/instance_usbhs.h"
389#include "instance/instance_afec0.h"
390#include "instance/instance_dacc.h"
391#include "instance/instance_acc.h"
392#include "instance/instance_icm.h"
393#include "instance/instance_isi.h"
394#include "instance/instance_gmac.h"
395#include "instance/instance_tc3.h"
396#include "instance/instance_spi1.h"
397#include "instance/instance_pwm1.h"
398#include "instance/instance_twihs2.h"
399#include "instance/instance_afec1.h"
400#include "instance/instance_mlb.h"
401#include "instance/instance_aes.h"
402#include "instance/instance_trng.h"
403#include "instance/instance_xdmac.h"
404#include "instance/instance_qspi.h"
405#include "instance/instance_smc.h"
406#include "instance/instance_sdramc.h"
407#include "instance/instance_matrix.h"
408#include "instance/instance_utmi.h"
409#include "instance/instance_pmc.h"
410#include "instance/instance_uart0.h"
411#include "instance/instance_chipid.h"
412#include "instance/instance_uart1.h"
413#include "instance/instance_efc.h"
414#include "instance/instance_pioa.h"
415#include "instance/instance_piob.h"
416#include "instance/instance_pioc.h"
417#include "instance/instance_piod.h"
418#include "instance/instance_pioe.h"
419#include "instance/instance_rstc.h"
420#include "instance/instance_supc.h"
421#include "instance/instance_rtt.h"
422#include "instance/instance_wdt.h"
423#include "instance/instance_rtc.h"
424#include "instance/instance_gpbr.h"
425#include "instance/instance_rswdt.h"
426#include "instance/instance_uart2.h"
427#include "instance/instance_uart3.h"
428#include "instance/instance_uart4.h"
429/*@}*/
430
431/* ************************************************************************** */
432/*   PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */
433/* ************************************************************************** */
434/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */
435/*@{*/
436
437#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
438#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
439#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
440#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
441#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
442#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
443#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
444#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
445#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
446#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
447#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
448#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
449#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
450#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
451#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
452#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
453#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
454#define ID_PIOE   (17) /**< \brief Parallel I/O Controller E (PIOE) */
455#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
456#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
457#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
458#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
459#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
460#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
461#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
462#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
463#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
464#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
465#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
466#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
467#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
468#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
469#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
470#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
471#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
472#define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
473#define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
474#define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
475#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
476#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
477#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
478#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
479#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
480#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
481#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
482#define ID_TC6    (47) /**< \brief Timer/Counter 6 (TC6) */
483#define ID_TC7    (48) /**< \brief Timer/Counter 7 (TC7) */
484#define ID_TC8    (49) /**< \brief Timer/Counter 8 (TC8) */
485#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
486#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
487#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
488#define ID_MLB    (53) /**< \brief MediaLB (MLB) */
489#define ID_AES    (56) /**< \brief AES (AES) */
490#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
491#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
492#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
493#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
494#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
495#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
496
497#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
498/*@}*/
499
500/* ************************************************************************** */
501/*   BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */
502/* ************************************************************************** */
503/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */
504/*@{*/
505
506#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
507#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
508#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
509#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
510#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
511#define TC1    (0x40010000U) /**< \brief (TC1   ) Base Address */
512#define TC2    (0x40014000U) /**< \brief (TC2   ) Base Address */
513#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
514#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
515#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
516#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
517#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
518#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
519#define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
520#define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
521#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
522#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
523#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
524#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
525#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
526#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
527#define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
528#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
529#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
530#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
531#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
532#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
533#define MLB    (0x40068000U) /**< \brief (MLB   ) Base Address */
534#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
535#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
536#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
537#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
538#define SMC    (0x40080000U) /**< \brief (SMC   ) Base Address */
539#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
540#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
541#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
542#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
543#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
544#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
545#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
546#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
547#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
548#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
549#define PIOC   (0x400E1200U) /**< \brief (PIOC  ) Base Address */
550#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
551#define PIOE   (0x400E1600U) /**< \brief (PIOE  ) Base Address */
552#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
553#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
554#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
555#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
556#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
557#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
558#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
559#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
560#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
561#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
562#else
563#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
564#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
565#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
566#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
567#define TC1    ((Tc     *)0x40010000U) /**< \brief (TC1   ) Base Address */
568#define TC2    ((Tc     *)0x40014000U) /**< \brief (TC2   ) Base Address */
569#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
570#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
571#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
572#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
573#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
574#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
575#define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
576#define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
577#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
578#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
579#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
580#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
581#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
582#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
583#define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
584#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
585#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
586#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
587#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
588#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
589#define MLB    ((Mlb    *)0x40068000U) /**< \brief (MLB   ) Base Address */
590#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
591#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
592#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
593#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
594#define SMC    ((Smc    *)0x40080000U) /**< \brief (SMC   ) Base Address */
595#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
596#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
597#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
598#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
599#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
600#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
601#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
602#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
603#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
604#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
605#define PIOC   ((Pio    *)0x400E1200U) /**< \brief (PIOC  ) Base Address */
606#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
607#define PIOE   ((Pio    *)0x400E1600U) /**< \brief (PIOE  ) Base Address */
608#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
609#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
610#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
611#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
612#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
613#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
614#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
615#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
616#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
617#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
618#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
619/*@}*/
620
621/* ************************************************************************** */
622/*   PIO DEFINITIONS FOR SAMV71Q21 */
623/* ************************************************************************** */
624/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */
625/*@{*/
626
627#include "pio/pio_samv71q21.h"
628/*@}*/
629
630/* ************************************************************************** */
631/*   MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */
632/* ************************************************************************** */
633
634#define IFLASH_SIZE             (0x200000u)
635#define IFLASH_PAGE_SIZE        (512u)
636#define IFLASH_LOCK_REGION_SIZE (8192u)
637#define IFLASH_NB_OF_PAGES      (4096u)
638#define IFLASH_NB_OF_LOCK_BITS  (128u)
639#define IRAM_SIZE               (0x60000u)
640
641#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
642#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
643#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
644#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
645#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
646#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
647#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
648#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
649#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
650#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
651#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
652#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
653#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM  base address */
654
655/* ************************************************************************** */
656/*   MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */
657/* ************************************************************************** */
658
659#define CHIP_JTAGID (0x05B3D03FUL)
660#define CHIP_CIDR   (0xA1220E00UL)
661#define CHIP_EXID   (0x00000002UL)
662
663/* ************************************************************************** */
664/*   ELECTRICAL DEFINITIONS FOR SAMV71Q21 */
665/* ************************************************************************** */
666
667/* %ATMEL_ELECTRICAL% */
668
669/* Device characteristics */
670#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
671#define CHIP_FREQ_SLCK_RC               (32000UL)
672#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
673#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
674#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
675#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
676#define CHIP_FREQ_CPU_MAX               (120000000UL)
677#define CHIP_FREQ_XTAL_32K              (32768UL)
678#define CHIP_FREQ_XTAL_12M              (12000000UL)
679
680/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
681#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
682#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
683#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
684#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
685#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
686#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
687
688#ifdef __cplusplus
689}
690#endif
691
692/*@}*/
693
694#endif /* _SAMV71Q21_ */
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