1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | #ifndef _SAMV71_TC_COMPONENT_ |
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31 | #define _SAMV71_TC_COMPONENT_ |
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32 | |
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33 | /* ============================================================================= */ |
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34 | /** SOFTWARE API DEFINITION FOR Timer Counter */ |
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35 | /* ============================================================================= */ |
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36 | /** \addtogroup SAMV71_TC Timer Counter */ |
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37 | /*@{*/ |
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38 | |
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39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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40 | /** \brief TcChannel hardware registers */ |
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41 | typedef struct { |
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42 | __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ |
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43 | __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ |
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44 | __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ |
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45 | __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ |
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46 | __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ |
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47 | __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ |
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48 | __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ |
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49 | __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ |
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50 | __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ |
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51 | __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ |
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52 | __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ |
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53 | __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ |
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54 | __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ |
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55 | __I uint32_t Reserved1[3]; |
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56 | } TcChannel; |
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57 | /** \brief Tc hardware registers */ |
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58 | #define TCCHANNEL_NUMBER 3 |
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59 | typedef struct { |
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60 | TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ |
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61 | __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ |
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62 | __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ |
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63 | __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ |
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64 | __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ |
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65 | __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ |
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66 | __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ |
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67 | __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ |
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68 | __I uint32_t Reserved1[2]; |
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69 | __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ |
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70 | __I uint32_t Reserved2[5]; |
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71 | __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ |
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72 | } Tc; |
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73 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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74 | /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ |
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75 | #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ |
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76 | #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ |
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77 | #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ |
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78 | /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ |
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79 | #define TC_CMR_TCCLKS_Pos 0 |
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80 | #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ |
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81 | #define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) |
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82 | #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ |
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83 | #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ |
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84 | #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ |
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85 | #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ |
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86 | #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ |
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87 | #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ |
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88 | #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ |
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89 | #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ |
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90 | #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ |
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91 | #define TC_CMR_BURST_Pos 4 |
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92 | #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ |
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93 | #define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) |
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94 | #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
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95 | #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ |
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96 | #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ |
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97 | #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ |
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98 | #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ |
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99 | #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ |
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100 | #define TC_CMR_ETRGEDG_Pos 8 |
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101 | #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ |
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102 | #define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) |
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103 | #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ |
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104 | #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
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105 | #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
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106 | #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
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107 | #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ |
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108 | #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ |
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109 | #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ |
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110 | #define TC_CMR_LDRA_Pos 16 |
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111 | #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ |
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112 | #define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) |
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113 | #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
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114 | #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ |
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115 | #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ |
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116 | #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ |
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117 | #define TC_CMR_LDRB_Pos 18 |
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118 | #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ |
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119 | #define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) |
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120 | #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
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121 | #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ |
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122 | #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ |
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123 | #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ |
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124 | #define TC_CMR_SBSMPLR_Pos 20 |
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125 | #define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ |
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126 | #define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) |
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127 | #define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ |
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128 | #define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ |
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129 | #define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ |
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130 | #define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ |
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131 | #define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ |
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132 | #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ |
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133 | #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ |
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134 | #define TC_CMR_EEVTEDG_Pos 8 |
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135 | #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ |
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136 | #define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) |
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137 | #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ |
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138 | #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ |
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139 | #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ |
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140 | #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ |
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141 | #define TC_CMR_EEVT_Pos 10 |
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142 | #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ |
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143 | #define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) |
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144 | #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ |
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145 | #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ |
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146 | #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ |
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147 | #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ |
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148 | #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ |
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149 | #define TC_CMR_WAVSEL_Pos 13 |
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150 | #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ |
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151 | #define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) |
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152 | #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ |
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153 | #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ |
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154 | #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ |
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155 | #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ |
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156 | #define TC_CMR_ACPA_Pos 16 |
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157 | #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ |
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158 | #define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) |
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159 | #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ |
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160 | #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ |
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161 | #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ |
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162 | #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ |
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163 | #define TC_CMR_ACPC_Pos 18 |
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164 | #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ |
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165 | #define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) |
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166 | #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ |
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167 | #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ |
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168 | #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ |
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169 | #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ |
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170 | #define TC_CMR_AEEVT_Pos 20 |
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171 | #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ |
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172 | #define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) |
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173 | #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ |
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174 | #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ |
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175 | #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ |
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176 | #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ |
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177 | #define TC_CMR_ASWTRG_Pos 22 |
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178 | #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ |
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179 | #define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) |
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180 | #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ |
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181 | #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ |
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182 | #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ |
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183 | #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ |
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184 | #define TC_CMR_BCPB_Pos 24 |
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185 | #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ |
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186 | #define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) |
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187 | #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ |
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188 | #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ |
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189 | #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ |
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190 | #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ |
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191 | #define TC_CMR_BCPC_Pos 26 |
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192 | #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ |
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193 | #define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) |
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194 | #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ |
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195 | #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ |
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196 | #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ |
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197 | #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ |
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198 | #define TC_CMR_BEEVT_Pos 28 |
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199 | #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ |
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200 | #define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) |
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201 | #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ |
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202 | #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ |
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203 | #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ |
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204 | #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ |
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205 | #define TC_CMR_BSWTRG_Pos 30 |
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206 | #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ |
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207 | #define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) |
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208 | #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ |
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209 | #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ |
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210 | #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ |
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211 | #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ |
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212 | /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ |
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213 | #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ |
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214 | #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ |
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215 | /* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ |
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216 | #define TC_RAB_RAB_Pos 0 |
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217 | #define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ |
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218 | /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ |
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219 | #define TC_CV_CV_Pos 0 |
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220 | #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ |
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221 | /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ |
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222 | #define TC_RA_RA_Pos 0 |
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223 | #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ |
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224 | #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) |
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225 | /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ |
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226 | #define TC_RB_RB_Pos 0 |
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227 | #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ |
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228 | #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) |
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229 | /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ |
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230 | #define TC_RC_RC_Pos 0 |
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231 | #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ |
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232 | #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) |
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233 | /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ |
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234 | #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ |
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235 | #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ |
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236 | #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ |
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237 | #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ |
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238 | #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ |
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239 | #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ |
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240 | #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ |
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241 | #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ |
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242 | #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ |
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243 | #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ |
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244 | #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ |
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245 | /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ |
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246 | #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ |
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247 | #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ |
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248 | #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ |
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249 | #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ |
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250 | #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ |
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251 | #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ |
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252 | #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ |
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253 | #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ |
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254 | /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ |
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255 | #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ |
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256 | #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ |
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257 | #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ |
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258 | #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ |
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259 | #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ |
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260 | #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ |
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261 | #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ |
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262 | #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ |
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263 | /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ |
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264 | #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ |
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265 | #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ |
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266 | #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ |
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267 | #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ |
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268 | #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ |
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269 | #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ |
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270 | #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ |
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271 | #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ |
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272 | /* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ |
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273 | #define TC_EMR_TRIGSRCA_Pos 0 |
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274 | #define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ |
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275 | #define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) |
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276 | #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ |
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277 | #define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ |
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278 | #define TC_EMR_TRIGSRCB_Pos 4 |
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279 | #define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ |
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280 | #define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) |
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281 | #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ |
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282 | #define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ |
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283 | #define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ |
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284 | /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ |
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285 | #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ |
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286 | /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ |
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287 | #define TC_BMR_TC0XC0S_Pos 0 |
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288 | #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ |
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289 | #define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) |
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290 | #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ |
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291 | #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ |
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292 | #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ |
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293 | #define TC_BMR_TC1XC1S_Pos 2 |
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294 | #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ |
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295 | #define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) |
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296 | #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ |
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297 | #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ |
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298 | #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ |
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299 | #define TC_BMR_TC2XC2S_Pos 4 |
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300 | #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ |
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301 | #define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) |
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302 | #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ |
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303 | #define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ |
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304 | #define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ |
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305 | #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ |
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306 | #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ |
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307 | #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ |
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308 | #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ |
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309 | #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ |
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310 | #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ |
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311 | #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ |
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312 | #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ |
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313 | #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ |
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314 | #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ |
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315 | #define TC_BMR_MAXFILT_Pos 20 |
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316 | #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ |
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317 | #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) |
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318 | /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ |
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319 | #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ |
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320 | #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ |
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321 | #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ |
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322 | /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ |
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323 | #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ |
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324 | #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ |
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325 | #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ |
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326 | /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ |
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327 | #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ |
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328 | #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ |
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329 | #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ |
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330 | /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ |
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331 | #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ |
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332 | #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ |
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333 | #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ |
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334 | #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ |
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335 | /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ |
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336 | #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ |
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337 | #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ |
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338 | /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ |
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339 | #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ |
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340 | #define TC_WPMR_WPKEY_Pos 8 |
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341 | #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ |
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342 | #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) |
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343 | #define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ |
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344 | /* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ |
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345 | #define TC_VER_VERSION_Pos 0 |
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346 | #define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ |
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347 | #define TC_VER_MFN_Pos 16 |
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348 | #define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ |
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349 | |
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350 | /*@}*/ |
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351 | |
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352 | |
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353 | #endif /* _SAMV71_TC_COMPONENT_ */ |
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