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sams70n20.h @ e1eeb883

Last change on this file since e1eeb883 was e1eeb883, checked in by Sebastian Huber <sebastian.huber@…>, on 01/12/16 at 14:34:31

bsp/atsam: Import SAM Software Package

Import selected files of the "SAM V71 / V70 / E70 / S70 Software
Package" obtained from the "SAMV71-XULT GNU Software Package 1.5".

Converted files via dos2unix before import.

Update #2529.

Property mode set to 100644

File size: 30.3 KB

Line
1	/* ---------------------------------------------------------------------------- */
2	/* Atmel Microcontroller Software Support */
3	/* SAM Software Package License */
4	/* ---------------------------------------------------------------------------- */
5	/* Copyright (c) 2015, Atmel Corporation */
6	/* */
7	/* All rights reserved. */
8	/* */
9	/* Redistribution and use in source and binary forms, with or without */
10	/* modification, are permitted provided that the following condition is met: */
11	/* */
12	/* - Redistributions of source code must retain the above copyright notice, */
13	/* this list of conditions and the disclaimer below. */
14	/* */
15	/* Atmel's name may not be used to endorse or promote products derived from */
16	/* this software without specific prior written permission. */
17	/* */
18	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28	/* ---------------------------------------------------------------------------- */
29
30	#ifndef _SAMS70N20_
31	#define _SAMS70N20_
32
33	/** \addtogroup SAMS70N20_definitions SAMS70N20 definitions
34	This file defines all structures and symbols for SAMS70N20:
35	- registers and bitfields
36	- peripheral base address
37	- peripheral ID
38	- PIO definitions
39	*/
40	/@{/
41
42	#ifdef __cplusplus
43	extern "C" {
44	#endif
45
46	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
47	#include <stdint.h>
48	#endif
49
50	/* ************************************************************************** */
51	/* CMSIS DEFINITIONS FOR SAMS70N20 */
52	/* ************************************************************************** */
53	/** \addtogroup SAMS70N20_cmsis CMSIS Definitions */
54	/@{/
55
56	/*< Interrupt Number Definition /
57	typedef enum IRQn
58	{
59	/**** Cortex-M7 Processor Exceptions Numbers ****************************/
60	NonMaskableInt_IRQn = -14, /*< 2 Non Maskable Interrupt /
61	HardFault_IRQn = -13, /*< 3 HardFault Interrupt /
62	MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt /
63	BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt /
64	UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt /
65	SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt /
66	DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt /
67	PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt /
68	SysTick_IRQn = -1, /*< 15 Cortex-M7 System Tick Interrupt /
69	/**** SAMS70N20 specific Interrupt Numbers *******************************/
70
71	SUPC_IRQn = 0, /*< 0 SAMS70N20 Supply Controller (SUPC) /
72	RSTC_IRQn = 1, /*< 1 SAMS70N20 Reset Controller (RSTC) /
73	RTC_IRQn = 2, /*< 2 SAMS70N20 Real Time Clock (RTC) /
74	RTT_IRQn = 3, /*< 3 SAMS70N20 Real Time Timer (RTT) /
75	WDT_IRQn = 4, /*< 4 SAMS70N20 Watchdog Timer (WDT) /
76	PMC_IRQn = 5, /*< 5 SAMS70N20 Power Management Controller (PMC) /
77	EFC_IRQn = 6, /*< 6 SAMS70N20 Enhanced Embedded Flash Controller (EFC) /
78	UART0_IRQn = 7, /*< 7 SAMS70N20 UART 0 (UART0) /
79	UART1_IRQn = 8, /*< 8 SAMS70N20 UART 1 (UART1) /
80	PIOA_IRQn = 10, /*< 10 SAMS70N20 Parallel I/O Controller A (PIOA) /
81	PIOB_IRQn = 11, /*< 11 SAMS70N20 Parallel I/O Controller B (PIOB) /
82	USART0_IRQn = 13, /*< 13 SAMS70N20 USART 0 (USART0) /
83	USART1_IRQn = 14, /*< 14 SAMS70N20 USART 1 (USART1) /
84	USART2_IRQn = 15, /*< 15 SAMS70N20 USART 2 (USART2) /
85	PIOD_IRQn = 16, /*< 16 SAMS70N20 Parallel I/O Controller D (PIOD) /
86	HSMCI_IRQn = 18, /*< 18 SAMS70N20 Multimedia Card Interface (HSMCI) /
87	TWIHS0_IRQn = 19, /*< 19 SAMS70N20 Two Wire Interface 0 HS (TWIHS0) /
88	TWIHS1_IRQn = 20, /*< 20 SAMS70N20 Two Wire Interface 1 HS (TWIHS1) /
89	SPI0_IRQn = 21, /*< 21 SAMS70N20 Serial Peripheral Interface 0 (SPI0) /
90	SSC_IRQn = 22, /*< 22 SAMS70N20 Synchronous Serial Controller (SSC) /
91	TC0_IRQn = 23, /*< 23 SAMS70N20 Timer/Counter 0 (TC0) /
92	TC1_IRQn = 24, /*< 24 SAMS70N20 Timer/Counter 1 (TC1) /
93	TC2_IRQn = 25, /*< 25 SAMS70N20 Timer/Counter 2 (TC2) /
94	AFEC0_IRQn = 29, /*< 29 SAMS70N20 Analog Front End 0 (AFEC0) /
95	DACC_IRQn = 30, /*< 30 SAMS70N19 Digital To Analog Converter (DACC) /
96	PWM0_IRQn = 31, /*< 31 SAMS70N20 Pulse Width Modulation 0 (PWM0) /
97	ICM_IRQn = 32, /*< 32 SAMS70N20 Integrity Check Monitor (ICM) /
98	ACC_IRQn = 33, /*< 33 SAMS70N20 Analog Comparator (ACC) /
99	USBHS_IRQn = 34, /*< 34 SAMS70N20 USB Host / Device Controller (USBHS) /
100	AFEC1_IRQn = 40, /*< 40 SAMS70N20 Analog Front End 1 (AFEC1) /
101	TWIHS2_IRQn = 41, /*< 41 SAMS70N20 Two Wire Interface 2 HS (TWIHS2) /
102	SPI1_IRQn = 42, /*< 42 SAMS70N20 Serial Peripheral Interface 1 (SPI1) /
103	QSPI_IRQn = 43, /*< 43 SAMS70N20 Quad I/O Serial Peripheral Interface (QSPI) /
104	UART2_IRQn = 44, /*< 44 SAMS70N20 UART 2 (UART2) /
105	UART3_IRQn = 45, /*< 45 SAMS70N20 UART 3 (UART3) /
106	UART4_IRQn = 46, /*< 46 SAMS70N20 UART 4 (UART4) /
107	TC9_IRQn = 50, /*< 50 SAMS70N20 Timer/Counter 9 (TC9) /
108	TC10_IRQn = 51, /*< 51 SAMS70N20 Timer/Counter 10 (TC10) /
109	TC11_IRQn = 52, /*< 52 SAMS70N20 Timer/Counter 11 (TC11) /
110	AES_IRQn = 56, /*< 56 SAMS70N20 AES (AES) /
111	TRNG_IRQn = 57, /*< 57 SAMS70N20 True Random Generator (TRNG) /
112	XDMAC_IRQn = 58, /*< 58 SAMS70N20 DMA (XDMAC) /
113	ISI_IRQn = 59, /*< 59 SAMS70N20 Camera Interface (ISI) /
114	PWM1_IRQn = 60, /*< 60 SAMS70N20 Pulse Width Modulation 1 (PWM1) /
115	RSWDT_IRQn = 63, /*< 63 SAMS70N20 Reinforced Secure Watchdog Timer (RSWDT) /
116
117	PERIPH_COUNT_IRQn = 64 /*< Number of peripheral IDs /
118	} IRQn_Type;
119
120	typedef struct _DeviceVectors
121	{
122	/* Stack pointer */
123	void* pvStack;
124
125	/* Cortex-M handlers */
126	void* pfnReset_Handler;
127	void* pfnNMI_Handler;
128	void* pfnHardFault_Handler;
129	void* pfnMemManage_Handler;
130	void* pfnBusFault_Handler;
131	void* pfnUsageFault_Handler;
132	void* pfnReserved1_Handler;
133	void* pfnReserved2_Handler;
134	void* pfnReserved3_Handler;
135	void* pfnReserved4_Handler;
136	void* pfnSVC_Handler;
137	void* pfnDebugMon_Handler;
138	void* pfnReserved5_Handler;
139	void* pfnPendSV_Handler;
140	void* pfnSysTick_Handler;
141
142	/* Peripheral handlers */
143	void* pfnSUPC_Handler; /* 0 Supply Controller */
144	void* pfnRSTC_Handler; /* 1 Reset Controller */
145	void* pfnRTC_Handler; /* 2 Real Time Clock */
146	void* pfnRTT_Handler; /* 3 Real Time Timer */
147	void* pfnWDT_Handler; /* 4 Watchdog Timer */
148	void* pfnPMC_Handler; /* 5 Power Management Controller */
149	void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
150	void* pfnUART0_Handler; /* 7 UART 0 */
151	void* pfnUART1_Handler; /* 8 UART 1 */
152	void* pvReserved9;
153	void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
154	void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
155	void* pvReserved12;
156	void* pfnUSART0_Handler; /* 13 USART 0 */
157	void* pfnUSART1_Handler; /* 14 USART 1 */
158	void* pfnUSART2_Handler; /* 15 USART 2 */
159	void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
160	void* pvReserved17;
161	void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
162	void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
163	void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
164	void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
165	void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
166	void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
167	void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
168	void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
169	void* pvReserved26;
170	void* pvReserved27;
171	void* pvReserved28;
172	void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
173	void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
174	void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
175	void* pfnICM_Handler; /* 32 Integrity Check Monitor */
176	void* pfnACC_Handler; /* 33 Analog Comparator */
177	void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
178	void* pvReserved35;
179	void* pvReserved36;
180	void* pvReserved37;
181	void* pvReserved38;
182	void* pvReserved39;
183	void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
184	void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
185	void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
186	void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
187	void* pfnUART2_Handler; /* 44 UART 2 */
188	void* pfnUART3_Handler; /* 45 UART 3 */
189	void* pfnUART4_Handler; /* 46 UART 4 */
190	void* pvReserved47;
191	void* pvReserved48;
192	void* pvReserved49;
193	void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
194	void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
195	void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
196	void* pvReserved53;
197	void* pvReserved54;
198	void* pvReserved55;
199	void* pfnAES_Handler; /* 56 AES */
200	void* pfnTRNG_Handler; /* 57 True Random Generator */
201	void* pfnXDMAC_Handler; /* 58 DMA */
202	void* pfnISI_Handler; /* 59 Camera Interface */
203	void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
204	void* pvReserved61;
205	void* pvReserved62;
206	void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
207	} DeviceVectors;
208
209	/* Cortex-M7 core handlers */
210	void Reset_Handler ( void );
211	void NMI_Handler ( void );
212	void HardFault_Handler ( void );
213	void MemManage_Handler ( void );
214	void BusFault_Handler ( void );
215	void UsageFault_Handler ( void );
216	void SVC_Handler ( void );
217	void DebugMon_Handler ( void );
218	void PendSV_Handler ( void );
219	void SysTick_Handler ( void );
220
221	/* Peripherals handlers */
222	void ACC_Handler ( void );
223	void AES_Handler ( void );
224	void AFEC0_Handler ( void );
225	void AFEC1_Handler ( void );
226	void DACC_Handler ( void );
227	void EFC_Handler ( void );
228	void HSMCI_Handler ( void );
229	void ICM_Handler ( void );
230	void ISI_Handler ( void );
231	void PIOA_Handler ( void );
232	void PIOB_Handler ( void );
233	void PIOD_Handler ( void );
234	void PMC_Handler ( void );
235	void PWM0_Handler ( void );
236	void PWM1_Handler ( void );
237	void QSPI_Handler ( void );
238	void RSTC_Handler ( void );
239	void RSWDT_Handler ( void );
240	void RTC_Handler ( void );
241	void RTT_Handler ( void );
242	void SPI0_Handler ( void );
243	void SPI1_Handler ( void );
244	void SSC_Handler ( void );
245	void SUPC_Handler ( void );
246	void TC0_Handler ( void );
247	void TC1_Handler ( void );
248	void TC2_Handler ( void );
249	void TC9_Handler ( void );
250	void TC10_Handler ( void );
251	void TC11_Handler ( void );
252	void TRNG_Handler ( void );
253	void TWIHS0_Handler ( void );
254	void TWIHS1_Handler ( void );
255	void TWIHS2_Handler ( void );
256	void UART0_Handler ( void );
257	void UART1_Handler ( void );
258	void UART2_Handler ( void );
259	void UART3_Handler ( void );
260	void UART4_Handler ( void );
261	void USART0_Handler ( void );
262	void USART1_Handler ( void );
263	void USART2_Handler ( void );
264	void USBHS_Handler ( void );
265	void WDT_Handler ( void );
266	void XDMAC_Handler ( void );
267
268	/**
269	* \brief Configuration of the Cortex-M7 Processor and Core Peripherals
270	*/
271
272	#define __CM7_REV 0x0000 /*< SAMS70N20 core revision number ([15:8] revision number, [7:0] patch number) /
273	#define __MPU_PRESENT 1 /*< SAMS70N20 does provide a MPU /
274	#define __NVIC_PRIO_BITS 3 /*< SAMS70N20 uses 3 Bits for the Priority Levels /
275	#define __FPU_PRESENT 1 /*< SAMS70N20 does provide a FPU /
276	#define __FPU_DP 1 /*< SAMS70N20 Double precision FPU /
277	#define __ICACHE_PRESENT 1 /*< SAMS70N20 does provide an Instruction Cache /
278	#define __DCACHE_PRESENT 1 /*< SAMS70N20 does provide a Data Cache /
279	#define __DTCM_PRESENT 1 /*< SAMS70N20 does provide a Data TCM /
280	#define __ITCM_PRESENT 1 /*< SAMS70N20 does provide an Instruction TCM /
281	#define __Vendor_SysTickConfig 0 /*< Set to 1 if different SysTick Config is used /
282
283	/*
284	* \brief CMSIS includes
285	*/
286
287	#include <core_cm7.h>
288	#if !defined DONT_USE_CMSIS_INIT
289	#include "system_sams70.h"
290	#endif /* DONT_USE_CMSIS_INIT */
291
292	/@}/
293
294	/* ************************************************************************** */
295	/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N20 */
296	/* ************************************************************************** */
297	/** \addtogroup SAMS70N20_api Peripheral Software API */
298	/@{/
299
300	#include "component/component_acc.h"
301	#include "component/component_aes.h"
302	#include "component/component_afec.h"
303	#include "component/component_chipid.h"
304	#include "component/component_dacc.h"
305	#include "component/component_efc.h"
306	#include "component/component_gpbr.h"
307	#include "component/component_hsmci.h"
308	#include "component/component_icm.h"
309	#include "component/component_isi.h"
310	#include "component/component_matrix.h"
311	#include "component/component_pio.h"
312	#include "component/component_pmc.h"
313	#include "component/component_pwm.h"
314	#include "component/component_qspi.h"
315	#include "component/component_rstc.h"
316	#include "component/component_rswdt.h"
317	#include "component/component_rtc.h"
318	#include "component/component_rtt.h"
319	#include "component/component_spi.h"
320	#include "component/component_ssc.h"
321	#include "component/component_supc.h"
322	#include "component/component_tc.h"
323	#include "component/component_trng.h"
324	#include "component/component_twihs.h"
325	#include "component/component_uart.h"
326	#include "component/component_usart.h"
327	#include "component/component_usbhs.h"
328	#include "component/component_utmi.h"
329	#include "component/component_wdt.h"
330	#include "component/component_xdmac.h"
331	/@}/
332
333	/* ************************************************************************** */
334	/* REGISTER ACCESS DEFINITIONS FOR SAMS70N20 */
335	/* ************************************************************************** */
336	/** \addtogroup SAMS70N20_reg Registers Access Definitions */
337	/@{/
338
339	#include "instance/instance_hsmci.h"
340	#include "instance/instance_ssc.h"
341	#include "instance/instance_spi0.h"
342	#include "instance/instance_tc0.h"
343	#include "instance/instance_twihs0.h"
344	#include "instance/instance_twihs1.h"
345	#include "instance/instance_pwm0.h"
346	#include "instance/instance_usart0.h"
347	#include "instance/instance_usart1.h"
348	#include "instance/instance_usart2.h"
349	#include "instance/instance_usbhs.h"
350	#include "instance/instance_afec0.h"
351	#include "instance/instance_dacc.h"
352	#include "instance/instance_acc.h"
353	#include "instance/instance_icm.h"
354	#include "instance/instance_isi.h"
355	#include "instance/instance_tc3.h"
356	#include "instance/instance_spi1.h"
357	#include "instance/instance_pwm1.h"
358	#include "instance/instance_twihs2.h"
359	#include "instance/instance_afec1.h"
360	#include "instance/instance_aes.h"
361	#include "instance/instance_trng.h"
362	#include "instance/instance_xdmac.h"
363	#include "instance/instance_qspi.h"
364	#include "instance/instance_matrix.h"
365	#include "instance/instance_utmi.h"
366	#include "instance/instance_pmc.h"
367	#include "instance/instance_uart0.h"
368	#include "instance/instance_chipid.h"
369	#include "instance/instance_uart1.h"
370	#include "instance/instance_efc.h"
371	#include "instance/instance_pioa.h"
372	#include "instance/instance_piob.h"
373	#include "instance/instance_piod.h"
374	#include "instance/instance_rstc.h"
375	#include "instance/instance_supc.h"
376	#include "instance/instance_rtt.h"
377	#include "instance/instance_wdt.h"
378	#include "instance/instance_rtc.h"
379	#include "instance/instance_gpbr.h"
380	#include "instance/instance_rswdt.h"
381	#include "instance/instance_uart2.h"
382	#include "instance/instance_uart3.h"
383	#include "instance/instance_uart4.h"
384	/@}/
385
386	/* ************************************************************************** */
387	/* PERIPHERAL ID DEFINITIONS FOR SAMS70N20 */
388	/* ************************************************************************** */
389	/** \addtogroup SAMS70N20_id Peripheral Ids Definitions */
390	/@{/
391
392	#define ID_SUPC ( 0) /*< \brief Supply Controller (SUPC) /
393	#define ID_RSTC ( 1) /*< \brief Reset Controller (RSTC) /
394	#define ID_RTC ( 2) /*< \brief Real Time Clock (RTC) /
395	#define ID_RTT ( 3) /*< \brief Real Time Timer (RTT) /
396	#define ID_WDT ( 4) /*< \brief Watchdog Timer (WDT) /
397	#define ID_PMC ( 5) /*< \brief Power Management Controller (PMC) /
398	#define ID_EFC ( 6) /*< \brief Enhanced Embedded Flash Controller (EFC) /
399	#define ID_UART0 ( 7) /*< \brief UART 0 (UART0) /
400	#define ID_UART1 ( 8) /*< \brief UART 1 (UART1) /
401	#define ID_PIOA (10) /*< \brief Parallel I/O Controller A (PIOA) /
402	#define ID_PIOB (11) /*< \brief Parallel I/O Controller B (PIOB) /
403	#define ID_USART0 (13) /*< \brief USART 0 (USART0) /
404	#define ID_USART1 (14) /*< \brief USART 1 (USART1) /
405	#define ID_USART2 (15) /*< \brief USART 2 (USART2) /
406	#define ID_PIOD (16) /*< \brief Parallel I/O Controller D (PIOD) /
407	#define ID_HSMCI (18) /*< \brief Multimedia Card Interface (HSMCI) /
408	#define ID_TWIHS0 (19) /*< \brief Two Wire Interface 0 HS (TWIHS0) /
409	#define ID_TWIHS1 (20) /*< \brief Two Wire Interface 1 HS (TWIHS1) /
410	#define ID_SPI0 (21) /*< \brief Serial Peripheral Interface 0 (SPI0) /
411	#define ID_SSC (22) /*< \brief Synchronous Serial Controller (SSC) /
412	#define ID_TC0 (23) /*< \brief Timer/Counter 0 (TC0) /
413	#define ID_TC1 (24) /*< \brief Timer/Counter 1 (TC1) /
414	#define ID_TC2 (25) /*< \brief Timer/Counter 2 (TC2) /
415	#define ID_AFEC0 (29) /*< \brief Analog Front End 0 (AFEC0) /
416	#define ID_DACC (30) /*< \brief Digital To Analog Converter (DACC) /
417	#define ID_PWM0 (31) /*< \brief Pulse Width Modulation 0 (PWM0) /
418	#define ID_ICM (32) /*< \brief Integrity Check Monitor (ICM) /
419	#define ID_ACC (33) /*< \brief Analog Comparator (ACC) /
420	#define ID_USBHS (34) /*< \brief USB Host / Device Controller (USBHS) /
421	#define ID_AFEC1 (40) /*< \brief Analog Front End 1 (AFEC1) /
422	#define ID_TWIHS2 (41) /*< \brief Two Wire Interface 2 HS (TWIHS2) /
423	#define ID_SPI1 (42) /*< \brief Serial Peripheral Interface 1 (SPI1) /
424	#define ID_QSPI (43) /*< \brief Quad I/O Serial Peripheral Interface (QSPI) /
425	#define ID_UART2 (44) /*< \brief UART 2 (UART2) /
426	#define ID_UART3 (45) /*< \brief UART 3 (UART3) /
427	#define ID_UART4 (46) /*< \brief UART 4 (UART4) /
428	#define ID_TC9 (50) /*< \brief Timer/Counter 9 (TC9) /
429	#define ID_TC10 (51) /*< \brief Timer/Counter 10 (TC10) /
430	#define ID_TC11 (52) /*< \brief Timer/Counter 11 (TC11) /
431	#define ID_AES (56) /*< \brief AES (AES) /
432	#define ID_TRNG (57) /*< \brief True Random Generator (TRNG) /
433	#define ID_XDMAC (58) /*< \brief DMA (XDMAC) /
434	#define ID_ISI (59) /*< \brief Camera Interface (ISI) /
435	#define ID_PWM1 (60) /*< \brief Pulse Width Modulation 1 (PWM1) /
436	#define ID_RSWDT (63) /*< \brief Reinforced Secure Watchdog Timer (RSWDT) /
437
438	#define ID_PERIPH_COUNT (64) /*< \brief Number of peripheral IDs /
439	/@}/
440
441	/* ************************************************************************** */
442	/* BASE ADDRESS DEFINITIONS FOR SAMS70N20 */
443	/* ************************************************************************** */
444	/** \addtogroup SAMS70N20_base Peripheral Base Address Definitions */
445	/@{/
446
447	#if (defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
448	#define HSMCI (0x40000000U) /*< \brief (HSMCI ) Base Address /
449	#define SSC (0x40004000U) /*< \brief (SSC ) Base Address /
450	#define SPI0 (0x40008000U) /*< \brief (SPI0 ) Base Address /
451	#define TC0 (0x4000C000U) /*< \brief (TC0 ) Base Address /
452	#define TWIHS0 (0x40018000U) /*< \brief (TWIHS0) Base Address /
453	#define TWIHS1 (0x4001C000U) /*< \brief (TWIHS1) Base Address /
454	#define PWM0 (0x40020000U) /*< \brief (PWM0 ) Base Address /
455	#define USART0 (0x40024000U) /*< \brief (USART0) Base Address /
456	#define USART1 (0x40028000U) /*< \brief (USART1) Base Address /
457	#define USART2 (0x4002C000U) /*< \brief (USART2) Base Address /
458	#define USBHS (0x40038000U) /*< \brief (USBHS ) Base Address /
459	#define AFEC0 (0x4003C000U) /*< \brief (AFEC0 ) Base Address /
460	#define DACC (0x40040000U) /*< \brief (DACC ) Base Address /
461	#define ACC (0x40044000U) /*< \brief (ACC ) Base Address /
462	#define ICM (0x40048000U) /*< \brief (ICM ) Base Address /
463	#define ISI (0x4004C000U) /*< \brief (ISI ) Base Address /
464	#define TC3 (0x40054000U) /*< \brief (TC3 ) Base Address /
465	#define SPI1 (0x40058000U) /*< \brief (SPI1 ) Base Address /
466	#define PWM1 (0x4005C000U) /*< \brief (PWM1 ) Base Address /
467	#define TWIHS2 (0x40060000U) /*< \brief (TWIHS2) Base Address /
468	#define AFEC1 (0x40064000U) /*< \brief (AFEC1 ) Base Address /
469	#define AES (0x4006C000U) /*< \brief (AES ) Base Address /
470	#define TRNG (0x40070000U) /*< \brief (TRNG ) Base Address /
471	#define XDMAC (0x40078000U) /*< \brief (XDMAC ) Base Address /
472	#define QSPI (0x4007C000U) /*< \brief (QSPI ) Base Address /
473	#define MATRIX (0x40088000U) /*< \brief (MATRIX) Base Address /
474	#define UTMI (0x400E0400U) /*< \brief (UTMI ) Base Address /
475	#define PMC (0x400E0600U) /*< \brief (PMC ) Base Address /
476	#define UART0 (0x400E0800U) /*< \brief (UART0 ) Base Address /
477	#define CHIPID (0x400E0940U) /*< \brief (CHIPID) Base Address /
478	#define UART1 (0x400E0A00U) /*< \brief (UART1 ) Base Address /
479	#define EFC (0x400E0C00U) /*< \brief (EFC ) Base Address /
480	#define PIOA (0x400E0E00U) /*< \brief (PIOA ) Base Address /
481	#define PIOB (0x400E1000U) /*< \brief (PIOB ) Base Address /
482	#define PIOD (0x400E1400U) /*< \brief (PIOD ) Base Address /
483	#define RSTC (0x400E1800U) /*< \brief (RSTC ) Base Address /
484	#define SUPC (0x400E1810U) /*< \brief (SUPC ) Base Address /
485	#define RTT (0x400E1830U) /*< \brief (RTT ) Base Address /
486	#define WDT (0x400E1850U) /*< \brief (WDT ) Base Address /
487	#define RTC (0x400E1860U) /*< \brief (RTC ) Base Address /
488	#define GPBR (0x400E1890U) /*< \brief (GPBR ) Base Address /
489	#define RSWDT (0x400E1900U) /*< \brief (RSWDT ) Base Address /
490	#define UART2 (0x400E1A00U) /*< \brief (UART2 ) Base Address /
491	#define UART3 (0x400E1C00U) /*< \brief (UART3 ) Base Address /
492	#define UART4 (0x400E1E00U) /*< \brief (UART4 ) Base Address /
493	#else
494	#define HSMCI ((Hsmci )0x40000000U) /< \brief (HSMCI ) Base Address /
495	#define SSC ((Ssc )0x40004000U) /< \brief (SSC ) Base Address /
496	#define SPI0 ((Spi )0x40008000U) /< \brief (SPI0 ) Base Address /
497	#define TC0 ((Tc )0x4000C000U) /< \brief (TC0 ) Base Address /
498	#define TWIHS0 ((Twihs )0x40018000U) /< \brief (TWIHS0) Base Address /
499	#define TWIHS1 ((Twihs )0x4001C000U) /< \brief (TWIHS1) Base Address /
500	#define PWM0 ((Pwm )0x40020000U) /< \brief (PWM0 ) Base Address /
501	#define USART0 ((Usart )0x40024000U) /< \brief (USART0) Base Address /
502	#define USART1 ((Usart )0x40028000U) /< \brief (USART1) Base Address /
503	#define USART2 ((Usart )0x4002C000U) /< \brief (USART2) Base Address /
504	#define USBHS ((Usbhs )0x40038000U) /< \brief (USBHS ) Base Address /
505	#define AFEC0 ((Afec )0x4003C000U) /< \brief (AFEC0 ) Base Address /
506	#define DACC ((Dacc )0x40040000U) /< \brief (DACC ) Base Address /
507	#define ACC ((Acc )0x40044000U) /< \brief (ACC ) Base Address /
508	#define ICM ((Icm )0x40048000U) /< \brief (ICM ) Base Address /
509	#define ISI ((Isi )0x4004C000U) /< \brief (ISI ) Base Address /
510	#define TC3 ((Tc )0x40054000U) /< \brief (TC3 ) Base Address /
511	#define SPI1 ((Spi )0x40058000U) /< \brief (SPI1 ) Base Address /
512	#define PWM1 ((Pwm )0x4005C000U) /< \brief (PWM1 ) Base Address /
513	#define TWIHS2 ((Twihs )0x40060000U) /< \brief (TWIHS2) Base Address /
514	#define AFEC1 ((Afec )0x40064000U) /< \brief (AFEC1 ) Base Address /
515	#define AES ((Aes )0x4006C000U) /< \brief (AES ) Base Address /
516	#define TRNG ((Trng )0x40070000U) /< \brief (TRNG ) Base Address /
517	#define XDMAC ((Xdmac )0x40078000U) /< \brief (XDMAC ) Base Address /
518	#define QSPI ((Qspi )0x4007C000U) /< \brief (QSPI ) Base Address /
519	#define MATRIX ((Matrix )0x40088000U) /< \brief (MATRIX) Base Address /
520	#define UTMI ((Utmi )0x400E0400U) /< \brief (UTMI ) Base Address /
521	#define PMC ((Pmc )0x400E0600U) /< \brief (PMC ) Base Address /
522	#define UART0 ((Uart )0x400E0800U) /< \brief (UART0 ) Base Address /
523	#define CHIPID ((Chipid )0x400E0940U) /< \brief (CHIPID) Base Address /
524	#define UART1 ((Uart )0x400E0A00U) /< \brief (UART1 ) Base Address /
525	#define EFC ((Efc )0x400E0C00U) /< \brief (EFC ) Base Address /
526	#define PIOA ((Pio )0x400E0E00U) /< \brief (PIOA ) Base Address /
527	#define PIOB ((Pio )0x400E1000U) /< \brief (PIOB ) Base Address /
528	#define PIOD ((Pio )0x400E1400U) /< \brief (PIOD ) Base Address /
529	#define RSTC ((Rstc )0x400E1800U) /< \brief (RSTC ) Base Address /
530	#define SUPC ((Supc )0x400E1810U) /< \brief (SUPC ) Base Address /
531	#define RTT ((Rtt )0x400E1830U) /< \brief (RTT ) Base Address /
532	#define WDT ((Wdt )0x400E1850U) /< \brief (WDT ) Base Address /
533	#define RTC ((Rtc )0x400E1860U) /< \brief (RTC ) Base Address /
534	#define GPBR ((Gpbr )0x400E1890U) /< \brief (GPBR ) Base Address /
535	#define RSWDT ((Rswdt )0x400E1900U) /< \brief (RSWDT ) Base Address /
536	#define UART2 ((Uart )0x400E1A00U) /< \brief (UART2 ) Base Address /
537	#define UART3 ((Uart )0x400E1C00U) /< \brief (UART3 ) Base Address /
538	#define UART4 ((Uart )0x400E1E00U) /< \brief (UART4 ) Base Address /
539	#endif /* (defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
540	/@}/
541
542	/* ************************************************************************** */
543	/* PIO DEFINITIONS FOR SAMS70N20 */
544	/* ************************************************************************** */
545	/** \addtogroup SAMS70N20_pio Peripheral Pio Definitions */
546	/@{/
547
548	#include "pio/pio_sams70n20.h"
549	/@}/
550
551	/* ************************************************************************** */
552	/* MEMORY MAPPING DEFINITIONS FOR SAMS70N20 */
553	/* ************************************************************************** */
554
555	#define IFLASH_SIZE (0x100000u)
556	#define IFLASH_PAGE_SIZE (512u)
557	#define IFLASH_LOCK_REGION_SIZE (8192u)
558	#define IFLASH_NB_OF_PAGES (2048u)
559	#define IFLASH_NB_OF_LOCK_BITS (64u)
560	#define IRAM_SIZE (0x60000u)
561
562	#define QSPIMEM_ADDR (0x80000000u) /*< QSPI Memory base address /
563	#define AXIMX_ADDR (0xA0000000u) /*< AXI Bus Matrix base address /
564	#define ITCM_ADDR (0x00000000u) /*< Instruction Tightly Coupled Memory base address /
565	#define IFLASH_ADDR (0x00400000u) /*< Internal Flash base address /
566	#define IROM_ADDR (0x00800000u) /*< Internal ROM base address /
567	#define DTCM_ADDR (0x20000000u) /*< Data Tightly Coupled Memory base address /
568	#define IRAM_ADDR (0x20400000u) /*< Internal RAM base address /
569	#define EBI_CS0_ADDR (0x60000000u) /*< EBI Chip Select 0 base address /
570	#define EBI_CS1_ADDR (0x61000000u) /*< EBI Chip Select 1 base address /
571	#define EBI_CS2_ADDR (0x62000000u) /*< EBI Chip Select 2 base address /
572	#define EBI_CS3_ADDR (0x63000000u) /*< EBI Chip Select 3 base address /
573	#define SDRAM_CS_ADDR (0x70000000u) /*< SDRAM Chip Select base address /
574
575	/* ************************************************************************** */
576	/* MISCELLANEOUS DEFINITIONS FOR SAMS70N20 */
577	/* ************************************************************************** */
578
579	#define CHIP_JTAGID (0x05B3D03FUL)
580	#define CHIP_CIDR (0xA1120C00UL)
581	#define CHIP_EXID (0x00000001UL)
582
583	/* ************************************************************************** */
584	/* ELECTRICAL DEFINITIONS FOR SAMS70N20 */
585	/* ************************************************************************** */
586
587	/* %ATMEL_ELECTRICAL% */
588
589	/* Device characteristics */
590	#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
591	#define CHIP_FREQ_SLCK_RC (32000UL)
592	#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
593	#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
594	#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
595	#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
596	#define CHIP_FREQ_CPU_MAX (120000000UL)
597	#define CHIP_FREQ_XTAL_32K (32768UL)
598	#define CHIP_FREQ_XTAL_12M (12000000UL)
599
600	/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
601	#define CHIP_FREQ_FWS_0 (20000000UL) /*< \brief Maximum operating frequency when FWS is 0 /
602	#define CHIP_FREQ_FWS_1 (40000000UL) /*< \brief Maximum operating frequency when FWS is 1 /
603	#define CHIP_FREQ_FWS_2 (60000000UL) /*< \brief Maximum operating frequency when FWS is 2 /
604	#define CHIP_FREQ_FWS_3 (80000000UL) /*< \brief Maximum operating frequency when FWS is 3 /
605	#define CHIP_FREQ_FWS_4 (100000000UL) /*< \brief Maximum operating frequency when FWS is 4 /
606	#define CHIP_FREQ_FWS_5 (123000000UL) /*< \brief Maximum operating frequency when FWS is 5 /
607
608	#ifdef __cplusplus
609	}
610	#endif
611
612	/@}/
613
614	#endif /* _SAMS70N20_ */

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source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/sams70/sams70n20.h @ e1eeb883

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