source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/same70/same70n20.h @ e1eeb883

5
Last change on this file since e1eeb883 was e1eeb883, checked in by Sebastian Huber <sebastian.huber@…>, on 01/12/16 at 14:34:31

bsp/atsam: Import SAM Software Package

Import selected files of the "SAM V71 / V70 / E70 / S70 Software
Package" obtained from the "SAMV71-XULT GNU Software Package 1.5".

Converted files via dos2unix before import.

Update #2529.
  • Property mode set to 100644
File size: 31.5 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70N20_
31#define _SAME70N20_
32
33/** \addtogroup SAME70N20_definitions SAME70N20 definitions
34  This file defines all structures and symbols for SAME70N20:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAME70N20 */
52/* ************************************************************************** */
53/** \addtogroup SAME70N20_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAME70N20 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAME70N20 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAME70N20 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAME70N20 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAME70N20 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAME70N20 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAME70N20 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAME70N20 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAME70N20 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAME70N20 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAME70N20 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAME70N20 Parallel I/O Controller B (PIOB) */
82  USART0_IRQn          = 13, /**< 13 SAME70N20 USART 0 (USART0) */
83  USART1_IRQn          = 14, /**< 14 SAME70N20 USART 1 (USART1) */
84  USART2_IRQn          = 15, /**< 15 SAME70N20 USART 2 (USART2) */
85  PIOD_IRQn            = 16, /**< 16 SAME70N20 Parallel I/O Controller D (PIOD) */
86  HSMCI_IRQn           = 18, /**< 18 SAME70N20 Multimedia Card Interface (HSMCI) */
87  TWIHS0_IRQn          = 19, /**< 19 SAME70N20 Two Wire Interface 0 HS (TWIHS0) */
88  TWIHS1_IRQn          = 20, /**< 20 SAME70N20 Two Wire Interface 1 HS (TWIHS1) */
89  SPI0_IRQn            = 21, /**< 21 SAME70N20 Serial Peripheral Interface 0 (SPI0) */
90  SSC_IRQn             = 22, /**< 22 SAME70N20 Synchronous Serial Controller (SSC) */
91  TC0_IRQn             = 23, /**< 23 SAME70N20 Timer/Counter 0 (TC0) */
92  TC1_IRQn             = 24, /**< 24 SAME70N20 Timer/Counter 1 (TC1) */
93  TC2_IRQn             = 25, /**< 25 SAME70N20 Timer/Counter 2 (TC2) */
94  AFEC0_IRQn           = 29, /**< 29 SAME70N20 Analog Front End 0 (AFEC0) */
95  DACC_IRQn            = 30, /**< 30 SAME70N20 Digital To Analog Converter (DACC) */
96  PWM0_IRQn            = 31, /**< 31 SAME70N20 Pulse Width Modulation 0 (PWM0) */
97  ICM_IRQn             = 32, /**< 32 SAME70N20 Integrity Check Monitor (ICM) */
98  ACC_IRQn             = 33, /**< 33 SAME70N20 Analog Comparator (ACC) */
99  USBHS_IRQn           = 34, /**< 34 SAME70N20 USB Host / Device Controller (USBHS) */
100  MCAN0_IRQn           = 35, /**< 35 SAME70N20 MCAN Controller 0 (MCAN0) */
101  MCAN1_IRQn           = 37, /**< 37 SAME70N20 MCAN Controller 1 (MCAN1) */
102  GMAC_IRQn            = 39, /**< 39 SAME70N20 Ethernet MAC (GMAC) */
103  AFEC1_IRQn           = 40, /**< 40 SAME70N20 Analog Front End 1 (AFEC1) */
104  TWIHS2_IRQn          = 41, /**< 41 SAME70N20 Two Wire Interface 2 HS (TWIHS2) */
105  SPI1_IRQn            = 42, /**< 42 SAME70N20 Serial Peripheral Interface 1 (SPI1) */
106  QSPI_IRQn            = 43, /**< 43 SAME70N20 Quad I/O Serial Peripheral Interface (QSPI) */
107  UART2_IRQn           = 44, /**< 44 SAME70N20 UART 2 (UART2) */
108  UART3_IRQn           = 45, /**< 45 SAME70N20 UART 3 (UART3) */
109  UART4_IRQn           = 46, /**< 46 SAME70N20 UART 4 (UART4) */
110  TC9_IRQn             = 50, /**< 50 SAME70N20 Timer/Counter 9 (TC9) */
111  TC10_IRQn            = 51, /**< 51 SAME70N20 Timer/Counter 10 (TC10) */
112  TC11_IRQn            = 52, /**< 52 SAME70N20 Timer/Counter 11 (TC11) */
113  AES_IRQn             = 56, /**< 56 SAME70N20 AES (AES) */
114  TRNG_IRQn            = 57, /**< 57 SAME70N20 True Random Generator (TRNG) */
115  XDMAC_IRQn           = 58, /**< 58 SAME70N20 DMA (XDMAC) */
116  ISI_IRQn             = 59, /**< 59 SAME70N20 Camera Interface (ISI) */
117  PWM1_IRQn            = 60, /**< 60 SAME70N20 Pulse Width Modulation 1 (PWM1) */
118  RSWDT_IRQn           = 63, /**< 63 SAME70N20 Reinforced Secure Watchdog Timer (RSWDT) */
119
120  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
121} IRQn_Type;
122
123typedef struct _DeviceVectors
124{
125  /* Stack pointer */
126  void* pvStack;
127
128  /* Cortex-M handlers */
129  void* pfnReset_Handler;
130  void* pfnNMI_Handler;
131  void* pfnHardFault_Handler;
132  void* pfnMemManage_Handler;
133  void* pfnBusFault_Handler;
134  void* pfnUsageFault_Handler;
135  void* pfnReserved1_Handler;
136  void* pfnReserved2_Handler;
137  void* pfnReserved3_Handler;
138  void* pfnReserved4_Handler;
139  void* pfnSVC_Handler;
140  void* pfnDebugMon_Handler;
141  void* pfnReserved5_Handler;
142  void* pfnPendSV_Handler;
143  void* pfnSysTick_Handler;
144
145  /* Peripheral handlers */
146  void* pfnSUPC_Handler;   /*  0 Supply Controller */
147  void* pfnRSTC_Handler;   /*  1 Reset Controller */
148  void* pfnRTC_Handler;    /*  2 Real Time Clock */
149  void* pfnRTT_Handler;    /*  3 Real Time Timer */
150  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
151  void* pfnPMC_Handler;    /*  5 Power Management Controller */
152  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
153  void* pfnUART0_Handler;  /*  7 UART 0 */
154  void* pfnUART1_Handler;  /*  8 UART 1 */
155  void* pvReserved9;
156  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
157  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
158  void* pvReserved12;
159  void* pfnUSART0_Handler; /* 13 USART 0 */
160  void* pfnUSART1_Handler; /* 14 USART 1 */
161  void* pfnUSART2_Handler; /* 15 USART 2 */
162  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
163  void* pvReserved17;
164  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
165  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
166  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
167  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
168  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
169  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
170  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
171  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
172  void* pvReserved26;
173  void* pvReserved27;
174  void* pvReserved28;
175  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
176  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
177  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
178  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
179  void* pfnACC_Handler;    /* 33 Analog Comparator */
180  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
181  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
182  void* pvReserved36;
183  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
184  void* pvReserved38;
185  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
186  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
187  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
188  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
189  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
190  void* pfnUART2_Handler;  /* 44 UART 2 */
191  void* pfnUART3_Handler;  /* 45 UART 3 */
192  void* pfnUART4_Handler;  /* 46 UART 4 */
193  void* pvReserved47;
194  void* pvReserved48;
195  void* pvReserved49;
196  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
197  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
198  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
199  void* pvReserved53;
200  void* pvReserved54;
201  void* pvReserved55;
202  void* pfnAES_Handler;    /* 56 AES */
203  void* pfnTRNG_Handler;   /* 57 True Random Generator */
204  void* pfnXDMAC_Handler;  /* 58 DMA */
205  void* pfnISI_Handler;    /* 59 Camera Interface */
206  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
207  void* pvReserved61;
208  void* pvReserved62;
209  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
210} DeviceVectors;
211
212/* Cortex-M7 core handlers */
213void Reset_Handler      ( void );
214void NMI_Handler        ( void );
215void HardFault_Handler  ( void );
216void MemManage_Handler  ( void );
217void BusFault_Handler   ( void );
218void UsageFault_Handler ( void );
219void SVC_Handler        ( void );
220void DebugMon_Handler   ( void );
221void PendSV_Handler     ( void );
222void SysTick_Handler    ( void );
223
224/* Peripherals handlers */
225void ACC_Handler        ( void );
226void AES_Handler        ( void );
227void AFEC0_Handler      ( void );
228void AFEC1_Handler      ( void );
229void DACC_Handler       ( void );
230void EFC_Handler        ( void );
231void GMAC_Handler       ( void );
232void HSMCI_Handler      ( void );
233void ICM_Handler        ( void );
234void ISI_Handler        ( void );
235void MCAN0_Handler      ( void );
236void MCAN1_Handler      ( void );
237void PIOA_Handler       ( void );
238void PIOB_Handler       ( void );
239void PIOD_Handler       ( void );
240void PMC_Handler        ( void );
241void PWM0_Handler       ( void );
242void PWM1_Handler       ( void );
243void QSPI_Handler       ( void );
244void RSTC_Handler       ( void );
245void RSWDT_Handler      ( void );
246void RTC_Handler        ( void );
247void RTT_Handler        ( void );
248void SPI0_Handler       ( void );
249void SPI1_Handler       ( void );
250void SSC_Handler        ( void );
251void SUPC_Handler       ( void );
252void TC0_Handler        ( void );
253void TC1_Handler        ( void );
254void TC2_Handler        ( void );
255void TC9_Handler        ( void );
256void TC10_Handler       ( void );
257void TC11_Handler       ( void );
258void TRNG_Handler       ( void );
259void TWIHS0_Handler     ( void );
260void TWIHS1_Handler     ( void );
261void TWIHS2_Handler     ( void );
262void UART0_Handler      ( void );
263void UART1_Handler      ( void );
264void UART2_Handler      ( void );
265void UART3_Handler      ( void );
266void UART4_Handler      ( void );
267void USART0_Handler     ( void );
268void USART1_Handler     ( void );
269void USART2_Handler     ( void );
270void USBHS_Handler      ( void );
271void WDT_Handler        ( void );
272void XDMAC_Handler      ( void );
273
274/**
275 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
276 */
277
278#define __CM7_REV              0x0000 /**< SAME70N20 core revision number ([15:8] revision number, [7:0] patch number) */
279#define __MPU_PRESENT          1      /**< SAME70N20 does provide a MPU */
280#define __NVIC_PRIO_BITS       3      /**< SAME70N20 uses 3 Bits for the Priority Levels */
281#define __FPU_PRESENT          1      /**< SAME70N20 does provide a FPU                */
282#define __FPU_DP               1      /**< SAME70N20 Double precision FPU              */
283#define __ICACHE_PRESENT       1      /**< SAME70N20 does provide an Instruction Cache */
284#define __DCACHE_PRESENT       1      /**< SAME70N20 does provide a Data Cache         */
285#define __DTCM_PRESENT         1      /**< SAME70N20 does provide a Data TCM           */
286#define __ITCM_PRESENT         1      /**< SAME70N20 does provide an Instruction TCM   */
287#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
288
289/*
290 * \brief CMSIS includes
291 */
292
293#include <core_cm7.h>
294#if !defined DONT_USE_CMSIS_INIT
295#include "system_same70.h"
296#endif /* DONT_USE_CMSIS_INIT */
297
298/*@}*/
299
300/* ************************************************************************** */
301/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */
302/* ************************************************************************** */
303/** \addtogroup SAME70N20_api Peripheral Software API */
304/*@{*/
305
306#include "component/component_acc.h"
307#include "component/component_aes.h"
308#include "component/component_afec.h"
309#include "component/component_chipid.h"
310#include "component/component_dacc.h"
311#include "component/component_efc.h"
312#include "component/component_gmac.h"
313#include "component/component_gpbr.h"
314#include "component/component_hsmci.h"
315#include "component/component_icm.h"
316#include "component/component_isi.h"
317#include "component/component_matrix.h"
318#include "component/component_mcan.h"
319#include "component/component_pio.h"
320#include "component/component_pmc.h"
321#include "component/component_pwm.h"
322#include "component/component_qspi.h"
323#include "component/component_rstc.h"
324#include "component/component_rswdt.h"
325#include "component/component_rtc.h"
326#include "component/component_rtt.h"
327#include "component/component_spi.h"
328#include "component/component_ssc.h"
329#include "component/component_supc.h"
330#include "component/component_tc.h"
331#include "component/component_trng.h"
332#include "component/component_twihs.h"
333#include "component/component_uart.h"
334#include "component/component_usart.h"
335#include "component/component_usbhs.h"
336#include "component/component_utmi.h"
337#include "component/component_wdt.h"
338#include "component/component_xdmac.h"
339/*@}*/
340
341/* ************************************************************************** */
342/*   REGISTER ACCESS DEFINITIONS FOR SAME70N20 */
343/* ************************************************************************** */
344/** \addtogroup SAME70N20_reg Registers Access Definitions */
345/*@{*/
346
347#include "instance/instance_hsmci.h"
348#include "instance/instance_ssc.h"
349#include "instance/instance_spi0.h"
350#include "instance/instance_tc0.h"
351#include "instance/instance_twihs0.h"
352#include "instance/instance_twihs1.h"
353#include "instance/instance_pwm0.h"
354#include "instance/instance_usart0.h"
355#include "instance/instance_usart1.h"
356#include "instance/instance_usart2.h"
357#include "instance/instance_mcan0.h"
358#include "instance/instance_mcan1.h"
359#include "instance/instance_usbhs.h"
360#include "instance/instance_afec0.h"
361#include "instance/instance_dacc.h"
362#include "instance/instance_acc.h"
363#include "instance/instance_icm.h"
364#include "instance/instance_isi.h"
365#include "instance/instance_gmac.h"
366#include "instance/instance_tc3.h"
367#include "instance/instance_spi1.h"
368#include "instance/instance_pwm1.h"
369#include "instance/instance_twihs2.h"
370#include "instance/instance_afec1.h"
371#include "instance/instance_aes.h"
372#include "instance/instance_trng.h"
373#include "instance/instance_xdmac.h"
374#include "instance/instance_qspi.h"
375#include "instance/instance_matrix.h"
376#include "instance/instance_utmi.h"
377#include "instance/instance_pmc.h"
378#include "instance/instance_uart0.h"
379#include "instance/instance_chipid.h"
380#include "instance/instance_uart1.h"
381#include "instance/instance_efc.h"
382#include "instance/instance_pioa.h"
383#include "instance/instance_piob.h"
384#include "instance/instance_piod.h"
385#include "instance/instance_rstc.h"
386#include "instance/instance_supc.h"
387#include "instance/instance_rtt.h"
388#include "instance/instance_wdt.h"
389#include "instance/instance_rtc.h"
390#include "instance/instance_gpbr.h"
391#include "instance/instance_rswdt.h"
392#include "instance/instance_uart2.h"
393#include "instance/instance_uart3.h"
394#include "instance/instance_uart4.h"
395/*@}*/
396
397/* ************************************************************************** */
398/*   PERIPHERAL ID DEFINITIONS FOR SAME70N20 */
399/* ************************************************************************** */
400/** \addtogroup SAME70N20_id Peripheral Ids Definitions */
401/*@{*/
402
403#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
404#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
405#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
406#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
407#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
408#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
409#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
410#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
411#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
412#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
413#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
414#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
415#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
416#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
417#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
418#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
419#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
420#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
421#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
422#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
423#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
424#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
425#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
426#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
427#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
428#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
429#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
430#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
431#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
432#define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
433#define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
434#define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
435#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
436#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
437#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
438#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
439#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
440#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
441#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
442#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
443#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
444#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
445#define ID_AES    (56) /**< \brief AES (AES) */
446#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
447#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
448#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
449#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
450#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
451
452#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
453/*@}*/
454
455/* ************************************************************************** */
456/*   BASE ADDRESS DEFINITIONS FOR SAME70N20 */
457/* ************************************************************************** */
458/** \addtogroup SAME70N20_base Peripheral Base Address Definitions */
459/*@{*/
460
461#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
462#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
463#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
464#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
465#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
466#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
467#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
468#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
469#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
470#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
471#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
472#define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
473#define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
474#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
475#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
476#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
477#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
478#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
479#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
480#define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
481#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
482#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
483#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
484#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
485#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
486#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
487#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
488#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
489#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
490#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
491#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
492#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
493#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
494#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
495#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
496#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
497#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
498#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
499#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
500#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
501#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
502#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
503#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
504#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
505#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
506#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
507#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
508#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
509#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
510#else
511#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
512#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
513#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
514#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
515#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
516#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
517#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
518#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
519#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
520#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
521#define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
522#define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
523#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
524#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
525#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
526#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
527#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
528#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
529#define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
530#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
531#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
532#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
533#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
534#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
535#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
536#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
537#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
538#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
539#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
540#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
541#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
542#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
543#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
544#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
545#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
546#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
547#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
548#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
549#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
550#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
551#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
552#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
553#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
554#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
555#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
556#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
557#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
558#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
559#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
560/*@}*/
561
562/* ************************************************************************** */
563/*   PIO DEFINITIONS FOR SAME70N20 */
564/* ************************************************************************** */
565/** \addtogroup SAME70N20_pio Peripheral Pio Definitions */
566/*@{*/
567
568#include "pio/pio_same70n20.h"
569/*@}*/
570
571/* ************************************************************************** */
572/*   MEMORY MAPPING DEFINITIONS FOR SAME70N20 */
573/* ************************************************************************** */
574
575#define IFLASH_SIZE             (0x100000u)
576#define IFLASH_PAGE_SIZE        (512u)
577#define IFLASH_LOCK_REGION_SIZE (8192u)
578#define IFLASH_NB_OF_PAGES      (2048u)
579#define IFLASH_NB_OF_LOCK_BITS  (64u)
580#define IRAM_SIZE               (0x60000u)
581
582#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
583#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
584#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
585#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
586#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
587#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
588#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
589#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
590#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
591#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
592#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
593#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
594
595/* ************************************************************************** */
596/*   MISCELLANEOUS DEFINITIONS FOR SAME70N20 */
597/* ************************************************************************** */
598
599#define CHIP_JTAGID (0x05B3D03FUL)
600#define CHIP_CIDR   (0xA1020C00UL)
601#define CHIP_EXID   (0x00000001UL)
602
603/* ************************************************************************** */
604/*   ELECTRICAL DEFINITIONS FOR SAME70N20 */
605/* ************************************************************************** */
606
607/* %ATMEL_ELECTRICAL% */
608
609/* Device characteristics */
610#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
611#define CHIP_FREQ_SLCK_RC               (32000UL)
612#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
613#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
614#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
615#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
616#define CHIP_FREQ_CPU_MAX               (120000000UL)
617#define CHIP_FREQ_XTAL_32K              (32768UL)
618#define CHIP_FREQ_XTAL_12M              (12000000UL)
619
620/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
621#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
622#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
623#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
624#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
625#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
626#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
627
628#ifdef __cplusplus
629}
630#endif
631
632/*@}*/
633
634#endif /* _SAME70N20_ */
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