1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | #ifndef _SAME70_RSTC_COMPONENT_ |
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31 | #define _SAME70_RSTC_COMPONENT_ |
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32 | |
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33 | /* ============================================================================= */ |
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34 | /** SOFTWARE API DEFINITION FOR Reset Controller */ |
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35 | /* ============================================================================= */ |
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36 | /** \addtogroup SAME70_RSTC Reset Controller */ |
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37 | /*@{*/ |
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38 | |
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39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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40 | /** \brief Rstc hardware registers */ |
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41 | typedef struct { |
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42 | __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ |
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43 | __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ |
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44 | __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ |
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45 | } Rstc; |
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46 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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47 | /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ |
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48 | #define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ |
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49 | #define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ |
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50 | #define RSTC_CR_KEY_Pos 24 |
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51 | #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ |
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52 | #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) |
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53 | #define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ |
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54 | /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ |
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55 | #define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ |
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56 | #define RSTC_SR_RSTTYP_Pos 8 |
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57 | #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ |
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58 | #define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ |
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59 | #define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ |
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60 | #define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ |
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61 | #define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ |
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62 | #define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ |
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63 | #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ |
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64 | #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ |
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65 | /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ |
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66 | #define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ |
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67 | #define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ |
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68 | #define RSTC_MR_ERSTL_Pos 8 |
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69 | #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ |
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70 | #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) |
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71 | #define RSTC_MR_KEY_Pos 24 |
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72 | #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ |
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73 | #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) |
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74 | #define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ |
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75 | |
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76 | /*@}*/ |
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77 | |
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78 | |
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79 | #endif /* _SAME70_RSTC_COMPONENT_ */ |
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