source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/qspi.h @ 0fddefe

Last change on this file since 0fddefe was 0fddefe, checked in by Alexander Krutwig <alexander.krutwig@…>, on Jun 8, 2016 at 7:55:53 AM

bsp/atsam: Fix QSPI driver API

We support read/write of arbitrary buffers.

  • Property mode set to 100644
File size: 7.7 KB
Line 
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28/* ---------------------------------------------------------------------------- */
29
30
31/**
32 * \file
33 *
34 * Interface for Serial Peripheral Interface (SPI) controller.
35 *
36 */
37
38#ifndef _QSPI_
39#define _QSPI_
40/*----------------------------------------------------------------------------
41 *        Macros
42 *----------------------------------------------------------------------------*/
43
44/**
45 *
46 * Here are several macros which should be used when configuring a SPI
47 * peripheral.
48 *
49 * \section qspi_configuration_macros SPI Configuration Macros
50 * - \ref QSPI_PCS
51 * - \ref QSPI_SCBR
52 * - \ref QSPI_DLYBS
53 * - \ref QSPI_DLYBCT
54 */
55
56/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
57#define QSPI_SCBR(baudrate, masterClock) \
58        ((uint32_t) (masterClock / baudrate) << 8)
59
60/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
61#define QSPI_DLYBS(delay, masterClock) \
62        ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
63
64/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
65#define QSPI_DLYBCT(delay, masterClock) \
66        ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
67
68/*--------------------------------------------------------------------------- */
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/*----------------------------------------------------------------------------
75 *        Exported functions
76 *----------------------------------------------------------------------------*/
77
78/** \brief qspi access modes
79 */
80typedef enum {
81        CmdAccess = 0,
82        ReadAccess,
83        WriteAccess
84} Access_t;
85
86/** \brief qspi modes SPI or QSPI
87 */
88typedef enum {
89        SpiMode = QSPI_MR_SMM_SPI,
90        QspiMemMode = QSPI_MR_SMM_MEMORY
91} QspiMode_t;
92
93
94/** \brief qspi clock modes , regarding clock phase and clock polarity
95 */
96typedef enum {
97        ClockMode_00 = 0,
98        ClockMode_10,
99        ClockMode_01,
100        ClockMode_11
101} QspiClockMode_t;
102
103
104/** \brief qspi status codes
105 */
106typedef enum {
107        QSPI_SUCCESS = 0,
108        QSPI_BUSY,
109        QSPI_BUSY_SENDING,
110        QSPI_READ_ERROR,
111        QSPI_WRITE_ERROR,
112        QSPI_UNKNOWN_ERROR,
113        QSPI_INIT_ERROR,
114        QSPI_INPUT_ERROR,
115        QSPI_TOTAL_ERROR
116} QspidStatus_t;
117
118
119/** \brief qspi status regiter bits
120 */
121typedef enum {
122        IsReceived    = QSPI_SR_RDRF,
123        IsTxSent      = QSPI_SR_TDRE,
124        IsTxEmpty     = QSPI_SR_TXEMPTY,
125        IsOverrun     = QSPI_SR_OVRES,
126        IsCsRise      = QSPI_SR_CSR,
127        IsCsAsserted  = QSPI_SR_CSS,
128        IsEofInst     = QSPI_SR_INSTRE,
129        IsEnabled     = QSPI_SR_QSPIENS
130} QspiStatus_t;
131
132/** \brief qspi command structure
133 */
134typedef struct {
135        uint8_t       Instruction;
136        uint8_t       Option;
137} QspiMemCmd_t;
138
139/** \brief qspi buffer structure
140 */
141typedef struct {
142        uint32_t      TxDataSize;     /* Tx buffer size */
143        uint32_t      RxDataSize;     /* Rx buffer size */
144        const void    *pDataTx;       /* Tx buffer */
145        void          *pDataRx;       /* Rx buffer */
146} QspiBuffer_t;
147
148
149/** \brief qspi frame structure for QSPI mode
150 */
151typedef struct {
152        union _QspiInstFrame {
153                uint32_t val;
154                struct _QspiInstFrameBM {
155                        uint32_t bwidth: 3,         /** Width of QSPI Addr , inst data */
156                                         reserved0: 1,       /** Reserved*/
157                                         bInstEn: 1,        /** Enable Inst */
158                                         bAddrEn: 1,        /** Enable Address */
159                                         bOptEn: 1,         /** Enable Option */
160                                         bDataEn: 1,        /** Enable Data */
161                                         bOptLen: 2,        /** Option Length*/
162                                         bAddrLen: 1,       /** Addrs Length*/
163                                         reserved1: 1,       /** Option Length*/
164                                         bXfrType: 2,       /** Transfer type*/
165                                         bContinuesRead: 1, /** Continoues read mode*/
166                                         reserved2: 1,       /** Reserved*/
167                                         bDummyCycles: 5,   /**< Unicast hash match */
168                                         reserved3: 11;      /** Reserved*/
169                } bm;
170        } InstFrame;
171        uint32_t       Addr;
172} QspiInstFrame_t;
173
174/** \brief qspi driver structure
175 */
176typedef struct {
177        uint8_t           qspiId;         /* QSPI ID */
178        Qspi              *pQspiHw;       /* QSPI Hw instance */
179        QspiMode_t        qspiMode;       /* Qspi mode: SPI or QSPI */
180        QspiMemCmd_t      qspiCommand;    /* Qspi command structure*/
181        QspiBuffer_t      qspiBuffer;     /* Qspi buffer*/
182        QspiInstFrame_t   *pQspiFrame;    /* Qspi QSPI mode Fram register informations*/
183} Qspid_t;
184
185
186void QSPI_SwReset(Qspi *pQspi);
187
188void QSPI_Disable(Qspi *pQspi);
189
190void QSPI_Enable(Qspi *pQspi);
191
192QspidStatus_t QSPI_EndTransfer(Qspi *pQspi);
193
194uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus);
195
196void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode,
197                                                  uint32_t dwClockCfg);
198
199QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData);
200
201QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *
202                                                                 const pData, uint32_t NumOfBytes);
203
204QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData);
205
206QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData ,
207                                                                  uint32_t NumOfBytes);
208
209QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources);
210
211QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources);
212
213uint32_t QSPI_GetItMask(Qspi *pQspi);
214
215uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi);
216
217QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode,
218                                                                           uint32_t dwConfiguration);
219
220QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg);
221
222QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg);
223
224QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi,  uint8_t const KeepCfg);
225
226QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg,
227                                                                        uint8_t ScrambleFlag);
228
229QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite);
230
231#ifdef __cplusplus
232}
233#endif
234
235#endif /* #ifndef _QSPI_ */
236
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