[e1eeb883] | 1 | /* ---------------------------------------------------------------------------- */ |
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| 2 | /* Atmel Microcontroller Software Support */ |
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| 3 | /* SAM Software Package License */ |
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| 4 | /* ---------------------------------------------------------------------------- */ |
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| 5 | /* Copyright (c) 2015, Atmel Corporation */ |
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| 6 | /* */ |
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| 7 | /* All rights reserved. */ |
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| 8 | /* */ |
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| 9 | /* Redistribution and use in source and binary forms, with or without */ |
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| 10 | /* modification, are permitted provided that the following condition is met: */ |
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| 11 | /* */ |
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| 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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| 13 | /* this list of conditions and the disclaimer below. */ |
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| 14 | /* */ |
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| 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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| 16 | /* this software without specific prior written permission. */ |
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| 17 | /* */ |
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| 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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| 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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| 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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| 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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| 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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| 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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| 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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| 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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| 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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| 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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| 28 | /* ---------------------------------------------------------------------------- */ |
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| 29 | |
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| 30 | |
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| 31 | /** |
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| 32 | * \file |
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| 33 | * |
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| 34 | * Interface for Serial Peripheral Interface (SPI) controller. |
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| 35 | * |
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| 36 | */ |
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| 37 | |
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| 38 | #ifndef _QSPI_ |
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| 39 | #define _QSPI_ |
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| 40 | /*---------------------------------------------------------------------------- |
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| 41 | * Macros |
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| 42 | *----------------------------------------------------------------------------*/ |
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| 43 | |
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| 44 | /** |
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| 45 | * |
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| 46 | * Here are several macros which should be used when configuring a SPI |
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| 47 | * peripheral. |
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| 48 | * |
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| 49 | * \section qspi_configuration_macros SPI Configuration Macros |
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| 50 | * - \ref QSPI_PCS |
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| 51 | * - \ref QSPI_SCBR |
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| 52 | * - \ref QSPI_DLYBS |
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| 53 | * - \ref QSPI_DLYBCT |
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| 54 | */ |
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| 55 | |
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| 56 | /** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ |
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| 57 | #define QSPI_SCBR(baudrate, masterClock) \ |
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| 58 | ((uint32_t) (masterClock / baudrate) << 8) |
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| 59 | |
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| 60 | /** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ |
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| 61 | #define QSPI_DLYBS(delay, masterClock) \ |
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| 62 | ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) |
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| 63 | |
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| 64 | /** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ |
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| 65 | #define QSPI_DLYBCT(delay, masterClock) \ |
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| 66 | ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) |
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| 67 | |
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| 68 | /*--------------------------------------------------------------------------- */ |
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| 69 | |
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| 70 | #ifdef __cplusplus |
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| 71 | extern "C" { |
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| 72 | #endif |
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| 73 | |
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| 74 | /*---------------------------------------------------------------------------- |
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| 75 | * Exported functions |
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| 76 | *----------------------------------------------------------------------------*/ |
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| 77 | |
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| 78 | /** \brief qspi access modes |
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| 79 | */ |
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| 80 | typedef enum { |
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| 81 | CmdAccess = 0, |
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| 82 | ReadAccess, |
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| 83 | WriteAccess |
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| 84 | } Access_t; |
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| 85 | |
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| 86 | /** \brief qspi modes SPI or QSPI |
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| 87 | */ |
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| 88 | typedef enum { |
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| 89 | SpiMode = QSPI_MR_SMM_SPI, |
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| 90 | QspiMemMode = QSPI_MR_SMM_MEMORY |
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| 91 | } QspiMode_t; |
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| 92 | |
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| 93 | |
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| 94 | /** \brief qspi clock modes , regarding clock phase and clock polarity |
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| 95 | */ |
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| 96 | typedef enum { |
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| 97 | ClockMode_00 = 0, |
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| 98 | ClockMode_10, |
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| 99 | ClockMode_01, |
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| 100 | ClockMode_11 |
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| 101 | } QspiClockMode_t; |
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| 102 | |
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| 103 | |
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| 104 | /** \brief qspi status codes |
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| 105 | */ |
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| 106 | typedef enum { |
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| 107 | QSPI_SUCCESS = 0, |
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| 108 | QSPI_BUSY, |
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| 109 | QSPI_BUSY_SENDING, |
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| 110 | QSPI_READ_ERROR, |
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| 111 | QSPI_WRITE_ERROR, |
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| 112 | QSPI_UNKNOWN_ERROR, |
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| 113 | QSPI_INIT_ERROR, |
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| 114 | QSPI_INPUT_ERROR, |
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| 115 | QSPI_TOTAL_ERROR |
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| 116 | } QspidStatus_t; |
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| 117 | |
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| 118 | |
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| 119 | /** \brief qspi status regiter bits |
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| 120 | */ |
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| 121 | typedef enum { |
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| 122 | IsReceived = QSPI_SR_RDRF, |
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| 123 | IsTxSent = QSPI_SR_TDRE, |
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| 124 | IsTxEmpty = QSPI_SR_TXEMPTY, |
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| 125 | IsOverrun = QSPI_SR_OVRES, |
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| 126 | IsCsRise = QSPI_SR_CSR, |
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| 127 | IsCsAsserted = QSPI_SR_CSS, |
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| 128 | IsEofInst = QSPI_SR_INSTRE, |
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| 129 | IsEnabled = QSPI_SR_QSPIENS |
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| 130 | } QspiStatus_t; |
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| 131 | |
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| 132 | /** \brief qspi command structure |
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| 133 | */ |
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| 134 | typedef struct { |
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| 135 | uint8_t Instruction; |
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| 136 | uint8_t Option; |
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| 137 | } QspiMemCmd_t; |
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| 138 | |
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| 139 | /** \brief qspi buffer structure |
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| 140 | */ |
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| 141 | typedef struct { |
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| 142 | uint32_t TxDataSize; /* Tx buffer size */ |
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| 143 | uint32_t RxDataSize; /* Rx buffer size */ |
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[0fddefe] | 144 | const void *pDataTx; /* Tx buffer */ |
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| 145 | void *pDataRx; /* Rx buffer */ |
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[e1eeb883] | 146 | } QspiBuffer_t; |
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| 147 | |
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| 148 | |
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| 149 | /** \brief qspi frame structure for QSPI mode |
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| 150 | */ |
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| 151 | typedef struct { |
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| 152 | union _QspiInstFrame { |
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| 153 | uint32_t val; |
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| 154 | struct _QspiInstFrameBM { |
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| 155 | uint32_t bwidth: 3, /** Width of QSPI Addr , inst data */ |
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| 156 | reserved0: 1, /** Reserved*/ |
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| 157 | bInstEn: 1, /** Enable Inst */ |
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| 158 | bAddrEn: 1, /** Enable Address */ |
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| 159 | bOptEn: 1, /** Enable Option */ |
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| 160 | bDataEn: 1, /** Enable Data */ |
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| 161 | bOptLen: 2, /** Option Length*/ |
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| 162 | bAddrLen: 1, /** Addrs Length*/ |
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| 163 | reserved1: 1, /** Option Length*/ |
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| 164 | bXfrType: 2, /** Transfer type*/ |
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| 165 | bContinuesRead: 1, /** Continoues read mode*/ |
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| 166 | reserved2: 1, /** Reserved*/ |
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| 167 | bDummyCycles: 5, /**< Unicast hash match */ |
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| 168 | reserved3: 11; /** Reserved*/ |
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| 169 | } bm; |
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| 170 | } InstFrame; |
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| 171 | uint32_t Addr; |
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| 172 | } QspiInstFrame_t; |
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| 173 | |
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| 174 | /** \brief qspi driver structure |
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| 175 | */ |
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| 176 | typedef struct { |
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| 177 | uint8_t qspiId; /* QSPI ID */ |
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| 178 | Qspi *pQspiHw; /* QSPI Hw instance */ |
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| 179 | QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */ |
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| 180 | QspiMemCmd_t qspiCommand; /* Qspi command structure*/ |
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| 181 | QspiBuffer_t qspiBuffer; /* Qspi buffer*/ |
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| 182 | QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/ |
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| 183 | } Qspid_t; |
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| 184 | |
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| 185 | |
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| 186 | void QSPI_SwReset(Qspi *pQspi); |
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| 187 | |
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| 188 | void QSPI_Disable(Qspi *pQspi); |
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| 189 | |
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| 190 | void QSPI_Enable(Qspi *pQspi); |
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| 191 | |
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| 192 | QspidStatus_t QSPI_EndTransfer(Qspi *pQspi); |
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| 193 | |
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| 194 | uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus); |
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| 195 | |
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| 196 | void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, |
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| 197 | uint32_t dwClockCfg); |
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| 198 | |
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| 199 | QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData); |
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| 200 | |
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| 201 | QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t * |
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| 202 | const pData, uint32_t NumOfBytes); |
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| 203 | |
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| 204 | QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData); |
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| 205 | |
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| 206 | QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData , |
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| 207 | uint32_t NumOfBytes); |
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| 208 | |
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| 209 | QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources); |
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| 210 | |
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| 211 | QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources); |
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| 212 | |
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| 213 | uint32_t QSPI_GetItMask(Qspi *pQspi); |
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| 214 | |
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| 215 | uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi); |
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| 216 | |
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| 217 | QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, |
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| 218 | uint32_t dwConfiguration); |
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| 219 | |
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| 220 | QspidStatus_t QSPI_SendCommand(Qspid_t *pQspi, uint8_t const KeepCfg); |
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| 221 | |
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| 222 | QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspi, uint8_t const KeepCfg); |
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| 223 | |
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| 224 | QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspi, uint8_t const KeepCfg); |
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| 225 | |
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| 226 | QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspi, uint8_t const KeepCfg, |
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| 227 | uint8_t ScrambleFlag); |
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| 228 | |
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| 229 | QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite); |
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| 230 | |
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| 231 | #ifdef __cplusplus |
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| 232 | } |
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| 233 | #endif |
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| 234 | |
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| 235 | #endif /* #ifndef _QSPI_ */ |
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| 236 | |
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