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mpu.h @ f7f420e

Last change on this file since f7f420e was f7f420e, checked in by Christian Mauderer <Christian.Mauderer@…>, on 09/06/17 at 05:42:06

bsp/atsam: Fix MPU sections.

The nocache section has been hard coded which could lead to problems
when a bigger region should be used. Fix that.

The internal SRAM has not been set up correctly. A duplicate external
SDRAM has been set up instead.

Remove a lot of other hard coded sections too.

Property mode set to 100644

File size: 11.2 KB

Line
1	/* ---------------------------------------------------------------------------- */
2	/* Atmel Microcontroller Software Support */
3	/* SAM Software Package License */
4	/* ---------------------------------------------------------------------------- */
5	/* Copyright (c) 2015, Atmel Corporation */
6	/* */
7	/* All rights reserved. */
8	/* */
9	/* Redistribution and use in source and binary forms, with or without */
10	/* modification, are permitted provided that the following condition is met: */
11	/* */
12	/* - Redistributions of source code must retain the above copyright notice, */
13	/* this list of conditions and the disclaimer below. */
14	/* */
15	/* Atmel's name may not be used to endorse or promote products derived from */
16	/* this software without specific prior written permission. */
17	/* */
18	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28	/* ---------------------------------------------------------------------------- */
29
30	#ifndef _MPU_H_
31	#define _MPU_H_
32	#ifdef __rtems__
33	#include <bsp.h>
34	#endif /* __rtems__ */
35
36	/*----------------------------------------------------------------------------
37	* Definitions
38	----------------------------------------------------------------------------/
39	#define ARM_MODE_USR 0x10
40
41	#define PRIVILEGE_MODE 0
42	#define USER_MODE 1
43
44	#define MPU_DEFAULT_ITCM_REGION (1)
45	#define MPU_DEFAULT_IFLASH_REGION (2)
46	#define MPU_DEFAULT_DTCM_REGION (3)
47	#define MPU_DEFAULT_SRAM_REGION_1 (4)
48	#define MPU_DEFAULT_SRAM_REGION_2 (5)
49	#define MPU_PERIPHERALS_REGION (6)
50	#define MPU_EXT_EBI_REGION (7)
51	#define MPU_DEFAULT_SDRAM_REGION (8)
52	#define MPU_QSPIMEM_REGION (9)
53	#define MPU_USBHSRAM_REGION (10)
54	#if defined MPU_HAS_NOCACHE_REGION
55	#define MPU_NOCACHE_SRAM_REGION (11)
56	#endif
57	#define MPU_SYSTEM_REGION (12)
58
59	#define MPU_REGION_VALID (0x10)
60	#define MPU_REGION_ENABLE (0x01)
61	#define MPU_REGION_DISABLE (0x0)
62
63	#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos)
64	#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos)
65	#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
66
67
68	#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos)
69	#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos)
70	#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos)
71
72	#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos)
73
74	#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos)
75	#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos)
76	#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos)
77	#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos)
78	#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos)
79	#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos)
80	#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos)
81	#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos)
82
83	#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos)
84	#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos)
85	#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos)
86	#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos)
87	#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos)
88	#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos)
89	#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos)
90	#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos)
91
92	/* Default memory map
93	Address range Memory region Memory type Shareability Cache policy
94	0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
95	0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
96	0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
97	0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
98	0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
99	0xA0000000- 0xBFFFFFFF Device Device Shareable
100	0xC0000000- 0xDFFFFFFF Device Device Non Shareable
101	0xE0000000- 0xFFFFFFFF System - -
102	*/
103
104	/******* IFLASH memory macros *******************/
105	#ifdef __rtems__
106	#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin)
107	#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1)
108	#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin)
109	#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1)
110	#else /* !__rtems__ */
111	#define ITCM_START_ADDRESS 0x00000000UL
112	#define ITCM_END_ADDRESS 0x003FFFFFUL
113	#define IFLASH_START_ADDRESS 0x00400000UL
114	#define IFLASH_END_ADDRESS 0x005FFFFFUL
115	#endif /* __rtems__ */
116
117
118	#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
119	#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
120
121	#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
122	#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
123
124	/************** DTCM *****************************/
125	#ifdef __rtems__
126	#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin)
127	#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1)
128	#else /* !__rtems__ */
129	#define DTCM_START_ADDRESS 0x20000000UL
130	#define DTCM_END_ADDRESS 0x203FFFFFUL
131	#endif /* __rtems__ */
132
133
134	/***** SRAM memory macros *************************/
135
136	#ifdef __rtems__
137	#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
138	#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
139	#else /* !__rtems__ */
140	#define SRAM_START_ADDRESS 0x20400000UL
141	#define SRAM_END_ADDRESS 0x2045FFFFUL
142	#endif /* __rtems__ */
143
144	#ifndef __rtems__
145	#if defined MPU_HAS_NOCACHE_REGION
146	#define NOCACHE_SRAM_REGION_SIZE 0x1000
147	#endif
148	#endif /* __rtems__ */
149
150	/* Regions should be a 2^(N+1) where 4 < N < 31 */
151	#ifdef __rtems__
152	#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
153	#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
154	#else /* !__rtems__ */
155	#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
156	#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
157	#endif /* __rtems__ */
158
159	#if defined MPU_HAS_NOCACHE_REGION
160	#ifdef __rtems__
161	#define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
162	#define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
163	#define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
164	#else /* !__rtems__ */
165	#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
166	#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
167	#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
168	#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
169	#endif /* __rtems__ */
170	#else
171	#ifndef __rtems__
172	#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
173	#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
174	#endif /* __rtems__ */
175	#endif
176	/************ Peripherals memory region macros ******/
177	#define PERIPHERALS_START_ADDRESS 0x40000000UL
178	#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
179	#ifdef __rtems__
180	#define SYSTEM_START_ADDRESS 0xE0000000UL
181	#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL
182	#endif /* __rtems__ */
183
184	/***** Ext EBI memory macros *************************/
185	#define EXT_EBI_START_ADDRESS 0x60000000UL
186	#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
187
188	/***** Ext-SRAM memory macros *************************/
189	#ifdef __rtems__
190	#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
191	#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
192	#else /* !__rtems__ */
193	#define SDRAM_START_ADDRESS 0x70000000UL
194	#define SDRAM_END_ADDRESS 0x7FFFFFFFUL
195	#endif /* __rtems__ */
196
197	/***** QSPI macros *************************/
198	#ifdef __rtems__
199	#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin)
200	#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1)
201	#else /* !__rtems__ */
202	#define QSPI_START_ADDRESS 0x80000000UL
203	#define QSPI_END_ADDRESS 0x9FFFFFFFUL
204	#endif /* __rtems__ */
205
206	/************ USBHS_RAM region macros ****************/
207	#define USBHSRAM_START_ADDRESS 0xA0100000UL
208	#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
209
210	/*----------------------------------------------------------------------------
211	* Export functions
212	----------------------------------------------------------------------------/
213	void MPU_Enable(uint32_t dwMPUEnable);
214	void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
215	void MPU_SetRegionNum(uint32_t dwRegionNum);
216	void MPU_DisableRegion(void);
217	uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes);
218	void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
219	uint32_t dwRegionAttr);
220
221	#endif /* #ifndef _MMU_ */
222

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source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h @ f7f420e

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