source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h @ 891fa3e

5
Last change on this file since 891fa3e was 891fa3e, checked in by Alexander Krutwig <alexander.krutwig@…>, on 06/28/16 at 08:47:15

bsp/atsam: Add support for TCM
  • Property mode set to 100644
File size: 9.5 KB
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1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _MPU_H_
31#define _MPU_H_
32#ifdef __rtems__
33#include <bsp.h>
34#endif /* __rtems__ */
35
36/*----------------------------------------------------------------------------
37 *        Definitions
38 *----------------------------------------------------------------------------*/
39#define ARM_MODE_USR            0x10
40
41#define PRIVILEGE_MODE 0
42#define USER_MODE      1
43
44#define MPU_DEFAULT_ITCM_REGION                 (1)
45#define MPU_DEFAULT_IFLASH_REGION               (2)
46#define MPU_DEFAULT_DTCM_REGION                 (3)
47#define MPU_DEFAULT_SRAM_REGION_1               (4)
48#define MPU_DEFAULT_SRAM_REGION_2               (5)
49#define MPU_PERIPHERALS_REGION                  (6)
50#define MPU_EXT_EBI_REGION                      (7)
51#define MPU_DEFAULT_SDRAM_REGION                (8)
52#define MPU_QSPIMEM_REGION                      (9)
53#define MPU_USBHSRAM_REGION                     (10)
54#if defined MPU_HAS_NOCACHE_REGION
55        #define MPU_NOCACHE_SRAM_REGION                 (11)
56#endif
57
58#define MPU_REGION_VALID                        (0x10)
59#define MPU_REGION_ENABLE                       (0x01)
60#define MPU_REGION_DISABLE                      (0x0)
61
62#define MPU_ENABLE                              (0x1 << MPU_CTRL_ENABLE_Pos)
63#define MPU_HFNMIENA                            (0x1 << MPU_CTRL_HFNMIENA_Pos)
64#define MPU_PRIVDEFENA                          (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
65
66
67#define MPU_REGION_BUFFERABLE                   (0x01 << MPU_RASR_B_Pos)
68#define MPU_REGION_CACHEABLE                    (0x01 << MPU_RASR_C_Pos)
69#define MPU_REGION_SHAREABLE                    (0x01 << MPU_RASR_S_Pos)
70
71#define MPU_REGION_EXECUTE_NEVER                (0x01 << MPU_RASR_XN_Pos)
72
73#define MPU_AP_NO_ACCESS                        (0x00 << MPU_RASR_AP_Pos)
74#define MPU_AP_PRIVILEGED_READ_WRITE            (0x01 << MPU_RASR_AP_Pos)
75#define MPU_AP_UNPRIVILEGED_READONLY            (0x02 << MPU_RASR_AP_Pos)
76#define MPU_AP_FULL_ACCESS                      (0x03 << MPU_RASR_AP_Pos)
77#define MPU_AP_RES                              (0x04 << MPU_RASR_AP_Pos)
78#define MPU_AP_PRIVILEGED_READONLY              (0x05 << MPU_RASR_AP_Pos)
79#define MPU_AP_READONLY                         (0x06 << MPU_RASR_AP_Pos)
80#define MPU_AP_READONLY2                        (0x07 << MPU_RASR_AP_Pos)
81
82#define MPU_TEX_B000                            (0x01 << MPU_RASR_TEX_Pos)
83#define MPU_TEX_B001                            (0x01 << MPU_RASR_TEX_Pos)
84#define MPU_TEX_B010                            (0x01 << MPU_RASR_TEX_Pos)
85#define MPU_TEX_B011                            (0x01 << MPU_RASR_TEX_Pos)
86#define MPU_TEX_B100                            (0x01 << MPU_RASR_TEX_Pos)
87#define MPU_TEX_B101                            (0x01 << MPU_RASR_TEX_Pos)
88#define MPU_TEX_B110                            (0x01 << MPU_RASR_TEX_Pos)
89#define MPU_TEX_B111                            (0x01 << MPU_RASR_TEX_Pos)
90
91/* Default memory map
92   Address range          Memory region          Memory type      Shareability   Cache policy
93   0x00000000- 0x1FFFFFFF Code                   Normal           Non-shareable  WT
94   0x20000000- 0x3FFFFFFF SRAM                   Normal           Non-shareable  WBWA
95   0x40000000- 0x5FFFFFFF Peripheral             Device           Non-shareable  -
96   0x60000000- 0x7FFFFFFF RAM                    Normal           Non-shareable  WBWA
97   0x80000000- 0x9FFFFFFF RAM                    Normal           Non-shareable  WT
98   0xA0000000- 0xBFFFFFFF Device                 Device           Shareable
99   0xC0000000- 0xDFFFFFFF Device                 Device           Non Shareable
100   0xE0000000- 0xFFFFFFFF System                  -                     -
101   */
102
103/********* IFLASH memory macros *********************/
104#define ITCM_START_ADDRESS                  0x00000000UL
105#define ITCM_END_ADDRESS                    0x003FFFFFUL
106#define IFLASH_START_ADDRESS                0x00400000UL
107#define IFLASH_END_ADDRESS                  0x005FFFFFUL
108
109
110#define IFLASH_PRIVILEGE_START_ADDRESS      (IFLASH_START_ADDRESS)
111#define IFLASH_PRIVILEGE_END_ADDRESS        (IFLASH_START_ADDRESS + 0xFFF)
112
113#define IFLASH_UNPRIVILEGE_START_ADDRESS    (IFLASH_PRIVILEGE_END_ADDRESS + 1)
114#define IFLASH_UNPRIVILEGE_END_ADDRESS      (IFLASH_END_ADDRESS)
115
116/**************** DTCM  *******************************/
117#define DTCM_START_ADDRESS                  0x20000000UL
118#define DTCM_END_ADDRESS                    0x203FFFFFUL
119
120
121/******* SRAM memory macros ***************************/
122
123#define SRAM_START_ADDRESS                  0x20400000UL
124#define SRAM_END_ADDRESS                    0x2045FFFFUL
125
126#if defined MPU_HAS_NOCACHE_REGION
127        #define NOCACHE_SRAM_REGION_SIZE            0x1000
128#endif
129
130/* Regions should be a 2^(N+1)  where 4 < N < 31 */
131#ifdef __rtems__
132#define SRAM_FIRST_START_ADDRESS            ((uintptr_t) atsam_memory_sdram_begin)
133#define SRAM_FIRST_END_ADDRESS              ((uintptr_t) atsam_memory_sdram_end - 1)
134#else /* __rtems__ */
135#define SRAM_FIRST_START_ADDRESS            (SRAM_START_ADDRESS)
136#define SRAM_FIRST_END_ADDRESS              (SRAM_FIRST_START_ADDRESS + 0x3FFFF)        // (2^18) 256 KB
137#endif /* __rtems__ */
138
139#if defined MPU_HAS_NOCACHE_REGION
140#ifdef __rtems__
141        #define SRAM_NOCACHE_START_ADDRESS          ((uintptr_t) atsam_memory_nocache_begin)
142        #define SRAM_NOCACHE_END_ADDRESS            ((uintptr_t) atsam_memory_nocache_end - 1)
143#else /* __rtems__ */
144        #define SRAM_SECOND_START_ADDRESS           (SRAM_FIRST_END_ADDRESS+1)
145        #define SRAM_SECOND_END_ADDRESS             (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE)              // (2^17) 128 - 0x1000 KB
146        #define SRAM_NOCACHE_START_ADDRESS          (SRAM_SECOND_END_ADDRESS + 1)
147        #define SRAM_NOCACHE_END_ADDRESS            (SRAM_END_ADDRESS)
148#endif /* __rtems__ */
149#else
150#ifndef __rtems__
151        #define SRAM_SECOND_START_ADDRESS           (SRAM_FIRST_END_ADDRESS + 1)
152        #define SRAM_SECOND_END_ADDRESS             (SRAM_END_ADDRESS)                          // (2^17) 128 KB
153#endif /* __rtems__ */
154#endif
155/************** Peripherals memory region macros ********/
156#define PERIPHERALS_START_ADDRESS            0x40000000UL
157#define PERIPHERALS_END_ADDRESS              0x5FFFFFFFUL
158
159/******* Ext EBI memory macros ***************************/
160#define EXT_EBI_START_ADDRESS                0x60000000UL
161#define EXT_EBI_END_ADDRESS                  0x6FFFFFFFUL
162
163/******* Ext-SRAM memory macros ***************************/
164#define SDRAM_START_ADDRESS                  0x70000000UL
165#define SDRAM_END_ADDRESS                    0x7FFFFFFFUL
166
167/******* QSPI macros ***************************/
168#define QSPI_START_ADDRESS                   0x80000000UL
169#define QSPI_END_ADDRESS                     0x9FFFFFFFUL
170
171/************** USBHS_RAM region macros ******************/
172#define USBHSRAM_START_ADDRESS               0xA0100000UL
173#define USBHSRAM_END_ADDRESS                 0xA01FFFFFUL
174
175/*----------------------------------------------------------------------------
176 *        Export functions
177 *----------------------------------------------------------------------------*/
178void MPU_Enable(uint32_t dwMPUEnable);
179void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
180void MPU_SetRegionNum(uint32_t dwRegionNum);
181void MPU_DisableRegion(void);
182uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes);
183void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
184                                                uint32_t dwRegionAttr);
185
186#endif /* #ifndef _MMU_ */
187
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