1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /** |
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31 | * \file |
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32 | * |
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33 | * \section Purpose |
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34 | * |
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35 | * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. |
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36 | * |
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37 | * \section Usage |
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38 | * |
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39 | * -# Configurate the pins for AFEC. |
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40 | * -# Initialize the AFEC with AFEC_Initialize(). |
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41 | * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). |
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42 | * -# Select the active channel using AFEC_EnableChannel(). |
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43 | * -# Start the conversion with AFEC_StartConversion(). |
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44 | * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). |
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45 | * -# Finally, get the converted data using AFEC_GetConvertedData() or |
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46 | * AFEC_GetLastConvertedData(). |
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47 | * |
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48 | */ |
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49 | #ifndef _AFEC_ |
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50 | #define _AFEC_ |
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51 | |
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52 | /*---------------------------------------------------------------------------- |
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53 | * Headers |
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54 | *----------------------------------------------------------------------------*/ |
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55 | #include <assert.h> |
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56 | #include <stdint.h> |
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57 | |
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58 | /*------------------------------------------------------------------------------ |
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59 | * Definitions |
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60 | *------------------------------------------------------------------------------*/ |
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61 | |
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62 | /* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ |
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63 | #define AFEC_MR_SETTLING_Pos 20 |
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64 | #define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) |
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65 | /**< \brief (AFEC_MR) Trigger Selection */ |
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66 | #define AFEC_MR_SETTLING_AST3 (0x0u << 20) |
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67 | /**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */ |
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68 | #define AFEC_MR_SETTLING_AST5 (0x1u << 20) |
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69 | /**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */ |
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70 | #define AFEC_MR_SETTLING_AST9 (0x2u << 20) |
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71 | /**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/ |
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72 | #define AFEC_MR_SETTLING_AST17 (0x3u << 20) |
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73 | /**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/ |
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74 | |
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75 | /***************************** Single Trigger Mode ****************************/ |
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76 | #define AFEC_EMR_STM_Pos 25 |
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77 | #define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) |
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78 | /**< \brief (AFEC_EMR) Single Trigger Mode */ |
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79 | #define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) |
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80 | /**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to |
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81 | get an averaged result. */ |
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82 | #define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) |
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83 | /**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required |
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84 | to get an averaged value. */ |
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85 | |
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86 | /***************************** TAG of the AFEC_LDCR Register ******************/ |
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87 | #define AFEC_EMR_TAG_Pos 24 |
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88 | #define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) |
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89 | /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */ |
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90 | #define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) |
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91 | /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero |
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92 | in AFEC_LDCR. */ |
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93 | #define AFEC_EMR_TAG_APPENDS (0x1u << 24) |
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94 | /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel |
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95 | number to the conversion result in AFEC_LDCR register. */ |
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96 | |
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97 | /***************************** Compare All Channels ******************/ |
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98 | #define AFEC_EMR_CMPALL_Pos 9 |
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99 | #define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) |
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100 | /**< \brief (AFEC_EMR) Compare All Channels */ |
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101 | #define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) |
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102 | /**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in |
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103 | CMPSEL field is compared. */ |
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104 | #define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) |
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105 | /**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */ |
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106 | |
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107 | #define AFEC_ACR_PGA0_ON (0x1u << 2) |
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108 | #define AFEC_ACR_PGA1_ON (0x1u << 3) |
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109 | |
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110 | #ifdef __cplusplus |
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111 | extern "C" { |
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112 | #endif |
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113 | |
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114 | /*------------------------------------------------------------------------------ |
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115 | * Macros function of register access |
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116 | *------------------------------------------------------------------------------*/ |
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117 | |
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118 | #define AFEC_GetModeReg(pAFEC) ((pAFEC)->AFEC_MR) |
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119 | #define AFEC_SetModeReg(pAFEC, mode) ((pAFEC)->AFEC_MR = mode) |
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120 | |
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121 | #define AFEC_GetExtModeReg(pAFEC) ((pAFEC)->AFEC_EMR) |
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122 | #define AFEC_SetExtModeReg(pAFEC, mode) ((pAFEC)->AFEC_EMR = mode) |
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123 | |
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124 | #define AFEC_StartConversion(pAFEC) ((pAFEC)->AFEC_CR = AFEC_CR_START) |
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125 | |
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126 | #define AFEC_EnableChannel(pAFEC, dwChannel) {\ |
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127 | (pAFEC)->AFEC_CHER = (1 << (dwChannel));\ |
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128 | } |
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129 | |
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130 | #define AFEC_DisableChannel(pAFEC, dwChannel) {\ |
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131 | (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\ |
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132 | } |
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133 | |
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134 | #define AFEC_EnableIt(pAFEC, dwMode) {\ |
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135 | (pAFEC)->AFEC_IER = (dwMode);\ |
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136 | } |
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137 | |
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138 | #define AFEC_DisableIt(pAFEC, dwMode) {\ |
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139 | (pAFEC)->AFEC_IDR = (dwMode);\ |
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140 | } |
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141 | |
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142 | #define AFEC_SetChannelGain(pAFEC,dwMode) {\ |
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143 | (pAFEC)->AFEC_CGR = dwMode;\ |
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144 | } |
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145 | |
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146 | #define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY) |
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147 | |
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148 | #define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR) |
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149 | |
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150 | #define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk)) |
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151 | |
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152 | #define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR) |
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153 | |
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154 | #define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR) |
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155 | |
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156 | #define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR) |
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157 | |
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158 | /*------------------------------------------------------------------------------ |
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159 | * Exported functions |
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160 | *------------------------------------------------------------------------------*/ |
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161 | extern void AFEC_Initialize(Afec *pAFEC, uint32_t dwId); |
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162 | extern uint32_t AFEC_SetClock(Afec *pAFEC, uint32_t dwPres, uint32_t dwMck); |
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163 | extern void AFEC_SetTiming(Afec *pAFEC, uint32_t dwStartup, |
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164 | uint32_t dwTracking, |
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165 | uint32_t dwSettling); |
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166 | extern void AFEC_SetTrigger(Afec *pAFEC, uint32_t dwTrgSel); |
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167 | extern void AFEC_SetAnalogChange(Afec *pAFE, uint8_t bEnDis); |
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168 | extern void AFEC_SetSleepMode(Afec *pAFEC, uint8_t bEnDis); |
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169 | extern void AFEC_SetFastWakeup(Afec *pAFEC, uint8_t bEnDis); |
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170 | extern void AFEC_SetSequenceMode(Afec *pAFEC, uint8_t bEnDis); |
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171 | extern void AFEC_SetSequence(Afec *pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2); |
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172 | extern void AFEC_SetSequenceByList(Afec *pAFEC, uint8_t ucChList[], |
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173 | uint8_t ucNumCh); |
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174 | extern void AFEC_SetTagEnable(Afec *pAFEC, uint8_t bEnDis); |
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175 | extern void AFEC_SetCompareChannel(Afec *pAFEC, uint32_t dwChannel); |
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176 | extern void AFEC_SetCompareMode(Afec *pAFEC, uint32_t dwMode); |
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177 | extern void AFEC_SetComparisonWindow(Afec *pAFEC, uint32_t dwHi_Lo); |
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178 | extern uint8_t AFEC_CheckConfiguration(Afec *pAFEC, uint32_t dwMcK); |
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179 | extern uint32_t AFEC_GetConvertedData(Afec *pAFEC, uint32_t dwChannel); |
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180 | extern void AFEC_SetStartupTime(Afec *pAFEC, uint32_t dwUs); |
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181 | extern void AFEC_SetTrackingTime(Afec *pAFEC, uint32_t dwNs); |
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182 | extern void AFEC_SetAnalogOffset(Afec *pAFE, uint32_t dwChannel, |
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183 | uint32_t aoffset); |
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184 | extern void AFEC_SetAnalogControl(Afec *pAFE, uint32_t control); |
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185 | #ifdef __cplusplus |
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186 | } |
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187 | #endif |
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188 | |
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189 | #endif /* #ifndef _AFEC_ */ |
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190 | |
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