1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | #ifndef SAMS7_CHIP_H |
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31 | #define SAMS7_CHIP_H |
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32 | |
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33 | #include "compiler.h" |
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34 | |
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35 | |
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36 | /************************************************* |
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37 | * Memory type and its attribute |
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38 | *************************************************/ |
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39 | #define SHAREABLE 1 |
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40 | #define NON_SHAREABLE 0 |
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41 | /********************************************************************************************************************************************************************* |
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42 | * Memory Type Definition Memory TEX attribute C attribute B attribute S attribute |
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43 | **********************************************************************************************************************************************************************/ |
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44 | |
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45 | #define STRONGLY_ORDERED_SHAREABLE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // |
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46 | #define SHAREABLE_DEVICE_TYPE ((0x00 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos)) // DO not care // |
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47 | #define INNER_OUTER_NORMAL_WT_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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48 | #define INNER_OUTER_NORMAL_WB_NWA_TYPE(x) ((0x00 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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49 | #define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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50 | #define INNER_OUTER_NORMAL_WB_RWA_TYPE(x) ((0x01 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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51 | #define NON_SHAREABLE_DEVICE_TYPE ((0x02 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos)) // DO not care // |
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52 | |
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53 | /* Normal memory attributes with outer capability rules to Non_Cacable */ |
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54 | |
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55 | #define INNER_NORMAL_NOCACHE_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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56 | #define INNER_NORMAL_WB_RWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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57 | #define INNER_NORMAL_WT_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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58 | #define INNER_NORMAL_WB_NWA_TYPE(x) ((0x04 << MPU_RASR_TEX_Pos) | (ENABLE << MPU_RASR_C_Pos) | (ENABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos)) |
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59 | |
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60 | /* SCB Interrupt Control State Register Definitions */ |
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61 | #ifndef SCB_VTOR_TBLBASE_Pos |
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62 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
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63 | #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
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64 | #endif |
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65 | |
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66 | |
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67 | /* |
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68 | * Peripherals |
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69 | */ |
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70 | #include "include/acc.h" |
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71 | #include "include/aes.h" |
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72 | #include "include/afec.h" |
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73 | #include "include/efc.h" |
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74 | #include "include/pio.h" |
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75 | #include "include/pio_it.h" |
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76 | #include "include/efc.h" |
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77 | #include "include/rstc.h" |
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78 | #include "include/mpu.h" |
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79 | #include "include/gmac.h" |
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80 | #include "include/gmacd.h" |
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81 | #include "include/video.h" |
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82 | #include "include/icm.h" |
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83 | #include "include/isi.h" |
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84 | #include "include/exceptions.h" |
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85 | #include "include/pio_capture.h" |
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86 | #include "include/rtc.h" |
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87 | #include "include/rtt.h" |
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88 | #include "include/tc.h" |
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89 | #include "include/timetick.h" |
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90 | #include "include/twi.h" |
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91 | #include "include/flashd.h" |
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92 | #include "include/pmc.h" |
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93 | #include "include/pwmc.h" |
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94 | #include "include/mcan.h" |
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95 | #include "include/supc.h" |
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96 | #include "include/usart.h" |
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97 | #include "include/uart.h" |
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98 | #include "include/isi.h" |
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99 | #include "include/hsmci.h" |
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100 | #include "include/ssc.h" |
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101 | #include "include/twi.h" |
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102 | #include "include/trng.h" |
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103 | #include "include/wdt.h" |
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104 | #include "include/spi.h" |
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105 | #include "include/qspi.h" |
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106 | #include "include/trace.h" |
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107 | #include "include/xdmac.h" |
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108 | #include "include/xdma_hardware_interface.h" |
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109 | #include "include/xdmad.h" |
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110 | #include "include/mcid.h" |
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111 | #include "include/twid.h" |
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112 | #include "include/spi_dma.h" |
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113 | #include "include/qspi_dma.h" |
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114 | #include "include/uart_dma.h" |
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115 | #include "include/usart_dma.h" |
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116 | #include "include/twid.h" |
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117 | #include "include/afe_dma.h" |
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118 | #include "include/dac_dma.h" |
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119 | #include "include/usbhs.h" |
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120 | |
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121 | #define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral(dwId) |
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122 | #define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral(dwId) |
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123 | |
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124 | #endif /* SAMS7_CHIP_H */ |
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