source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_memories.c @ e1eeb883

5
Last change on this file since e1eeb883 was e1eeb883, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 12, 2016 at 2:34:31 PM

bsp/atsam: Import SAM Software Package

Import selected files of the "SAM V71 / V70 / E70 / S70 Software
Package" obtained from the "SAMV71-XULT GNU Software Package 1.5".

Converted files via dos2unix before import.

Update #2529.

  • Property mode set to 100644
File size: 9.1 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/**
31 * \file
32 *
33 * Implementation of memories configuration on board.
34 *
35 */
36
37/*----------------------------------------------------------------------------
38 *        Headers
39 *----------------------------------------------------------------------------*/
40#include "board.h"
41
42/*----------------------------------------------------------------------------
43 *        Exported functions
44 *----------------------------------------------------------------------------*/
45
46#define SDRAM_BA0 (1 << 20)
47#define SDRAM_BA1 (1 << 21)
48
49
50uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size)
51{
52        uint32_t i;
53        uint32_t ret = 1;
54        uint32_t *ptr32 = (uint32_t *) baseAddr;
55        uint16_t *ptr16 = (uint16_t *) baseAddr;
56        uint8_t *ptr8 = (uint8_t *) baseAddr;
57        /* Test for 55AA55AA/AA55AA55 pattern */
58        printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r");
59
60        for (i = 0; i < size; i ++) {
61                if (i & 1)
62                        ptr32[i] = 0x55AA55AA;
63                else
64                        ptr32[i] = 0xAA55AA55;
65
66                memory_barrier()
67        }
68
69        for (i = 0; i <  size; i++) {
70                if (i & 1) {
71                        if (ptr32[i] != 0x55AA55AA) {
72                                printf("-E- Expected:%x, read %x @ %x \n\r" ,
73                                           0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i));
74                                ret = 0;
75
76                        }
77                } else {
78                        if (ptr32[i] != 0xAA55AA55) {
79                                printf("-E- Expected:%x, read %x @ %x \n\r" ,
80                                           0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i));
81                                ret = 0;
82                        }
83                }
84        }
85
86        if (!ret) return ret;
87
88        printf(" Test for BYTE accessing... \n\r");
89
90        /* Test for BYTE accessing */
91        for (i = 0; i < size; i ++)
92                ptr8[i] = (uint8_t)(i & 0xFF);
93
94        for (i = 0; i <  size; i++) {
95                if (ptr8[i] != (uint8_t)(i & 0xFF))  {
96                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
97                                   (unsigned)(i & 0xFF), ptr8[i], (unsigned)(baseAddr + i));
98                        ret = 0;
99                }
100        }
101
102        if (!ret) return ret;
103
104        printf(" Test for WORD accessing... \n\r");
105
106        /* Test for WORD accessing */
107        for (i = 0; i < size / 2; i ++)
108                ptr16[i] = (uint16_t)(i & 0xFFFF);
109
110        for (i = 0; i <  size / 2; i++) {
111                if (ptr16[i] != (uint16_t)(i & 0xFFFF))  {
112                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
113                                   (unsigned)(i & 0xFFFF), ptr16[i], (unsigned)(baseAddr + i));
114                        ret = 0;
115                }
116        }
117
118        if (!ret) return ret;
119
120        printf(" Test for DWORD accessing... \n\r");
121
122        /* Test for DWORD accessing */
123        for (i = 0; i < size / 4; i ++) {
124                ptr32[i] = (uint32_t)(i & 0xFFFFFFFF);
125                memory_barrier()
126        }
127
128        for (i = 0; i <  size / 4; i++) {
129                if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF))  {
130                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
131                                   (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i));
132                        ret = 0;
133                }
134        }
135
136        return ret;
137}
138
139
140/**
141 * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access.
142 */
143
144
145void BOARD_ConfigureSdram(void)
146{
147        const Pin pinsSdram[] = {BOARD_SDRAM_PINS};
148        volatile uint32_t i;
149        volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR;
150
151        /* Configure PIO */
152        PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
153        PMC_EnablePeripheral(ID_SDRAMC);
154        MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN;
155
156        /* 1. SDRAM features must be set in the configuration register:
157        asynchronous timings (TRC, TRAS, etc.), number of columns, rows,
158        CAS latency, and the data bus width. */
159        SDRAMC->SDRAMC_CR =
160                SDRAMC_CR_NC_COL8      // 8 column bits
161                | SDRAMC_CR_NR_ROW11     // 12 row bits (4K)
162                | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3
163                | SDRAMC_CR_NB_BANK2     // 2 banks
164                | SDRAMC_CR_DBW          // 16 bit
165                | SDRAMC_CR_TWR(5)
166                | SDRAMC_CR_TRC_TRFC(13) // 63ns   min
167                | SDRAMC_CR_TRP(5)       // Command period (PRE to ACT) 21 ns min
168                | SDRAMC_CR_TRCD(
169                        5)      // Active Command to read/Write Command delay time 21ns min
170                | SDRAMC_CR_TRAS(9)      // Command period (ACT to PRE)  42ns min
171                | SDRAMC_CR_TXSR(15U);   // Exit self-refresh to active time  70ns Min
172
173        /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
174        strength (DS) and partial array self refresh (PASR) must be set in the
175        Low Power Register. */
176
177        /* 3. The SDRAM memory type must be set in the Memory Device Register.*/
178        SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
179
180        /* 4. A minimum pause of 200 ŠÌs is provided to precede any signal toggle.*/
181        for (i = 0; i < 100000; i++);
182
183        /* 5. (1)A NOP command is issued to the SDRAM devices. The application must
184        set Mode to 1 in the Mode Register and perform a write access to
185        any SDRAM address.*/
186        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
187        *pSdram = 0;
188
189        for (i = 0; i < 100000; i++);
190
191        /* 6. An All Banks Precharge command is issued to the SDRAM devices.
192        The application must set Mode to 2 in the Mode Register and perform a write
193        access to any SDRAM address. */
194        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
195        *pSdram = 0;
196
197        for (i = 0; i < 100000; i++);
198
199        /* 7. Eight auto-refresh (CBR) cycles are provided. The application must
200        set the Mode to 4 in the Mode Register and perform a write access to any
201        SDRAM location eight times.*/
202        for (i = 0; i < 8; i++) {
203                SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
204                *pSdram = 0;
205        }
206
207        for (i = 0; i < 100000; i++);
208
209        /*8. A Mode Register set (MRS) cycle is issued to program the parameters of
210        the SDRAM devices, in particular CAS latency and burst length. The
211        application must set Mode to 3 in the Mode Register and perform a write
212        access to the SDRAM. The write address must be chosen so that BA[1:0]
213        are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns,
214        4 banks) bank address, the SDRAM write access should be done at the address
215        0x70000000.*/
216        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
217        *pSdram = 0;
218
219        for (i = 0; i < 100000; i++);
220
221        /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS)
222        cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The
223        application must set Mode to 5 in the Mode Register and perform a write
224        access to the SDRAM. The write address must be chosen so that BA[1] or BA[0]
225        are set to 1.
226        For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank
227        address the SDRAM write access should be done at the address 0x70800000 or
228        0x70400000. */
229        //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
230        // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0;
231
232        /* 10. The application must go into Normal Mode, setting Mode to 0 in the
233        Mode Register and performing a write access at any location in the SDRAM. */
234        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
235        *pSdram = 0;
236
237        for (i = 0; i < 100000; i++);
238
239        /* 11. Write the refresh rate into the count field in the SDRAMC Refresh
240        Timer register. (Refresh rate = delay between refresh cycles).
241        The SDRAM device requires a refresh every 15.625 ŠÌs or 7.81 ŠÌs.
242        With a 100 MHz frequency, the Refresh Timer Counter Register must be set
243        with the value 1562(15.625 ŠÌs x 100 MHz) or 781(7.81 ŠÌs x 100 MHz). */
244        // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ŠÌs
245        /* ((32 x 10(^-3))/2048) x150 x (10^6) */
246        SDRAMC->SDRAMC_TR = 1562;
247        SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL;
248        /* After initialization, the SDRAM devices are fully functional. */
249}
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