source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_memories.c @ c354fac

5
Last change on this file since c354fac was c354fac, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 14, 2016 at 2:48:44 PM

bsp/atsam: Port SAM Software Package to RTEMS

Update #2529.

  • Property mode set to 100644
File size: 9.3 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/**
31 * \file
32 *
33 * Implementation of memories configuration on board.
34 *
35 */
36
37/*----------------------------------------------------------------------------
38 *        Headers
39 *----------------------------------------------------------------------------*/
40#ifndef __rtems__
41#include "board.h"
42#else /* __rtems__ */
43#include <chip.h>
44#include <include/board_memories.h>
45#endif /* __rtems__ */
46
47/*----------------------------------------------------------------------------
48 *        Exported functions
49 *----------------------------------------------------------------------------*/
50
51#define SDRAM_BA0 (1 << 20)
52#define SDRAM_BA1 (1 << 21)
53
54
55#ifndef __rtems__
56uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size)
57{
58        uint32_t i;
59        uint32_t ret = 1;
60        uint32_t *ptr32 = (uint32_t *) baseAddr;
61        uint16_t *ptr16 = (uint16_t *) baseAddr;
62        uint8_t *ptr8 = (uint8_t *) baseAddr;
63        /* Test for 55AA55AA/AA55AA55 pattern */
64        printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r");
65
66        for (i = 0; i < size; i ++) {
67                if (i & 1)
68                        ptr32[i] = 0x55AA55AA;
69                else
70                        ptr32[i] = 0xAA55AA55;
71
72                memory_barrier()
73        }
74
75        for (i = 0; i <  size; i++) {
76                if (i & 1) {
77                        if (ptr32[i] != 0x55AA55AA) {
78                                printf("-E- Expected:%x, read %x @ %x \n\r" ,
79                                           0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i));
80                                ret = 0;
81
82                        }
83                } else {
84                        if (ptr32[i] != 0xAA55AA55) {
85                                printf("-E- Expected:%x, read %x @ %x \n\r" ,
86                                           0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i));
87                                ret = 0;
88                        }
89                }
90        }
91
92        if (!ret) return ret;
93
94        printf(" Test for BYTE accessing... \n\r");
95
96        /* Test for BYTE accessing */
97        for (i = 0; i < size; i ++)
98                ptr8[i] = (uint8_t)(i & 0xFF);
99
100        for (i = 0; i <  size; i++) {
101                if (ptr8[i] != (uint8_t)(i & 0xFF))  {
102                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
103                                   (unsigned)(i & 0xFF), ptr8[i], (unsigned)(baseAddr + i));
104                        ret = 0;
105                }
106        }
107
108        if (!ret) return ret;
109
110        printf(" Test for WORD accessing... \n\r");
111
112        /* Test for WORD accessing */
113        for (i = 0; i < size / 2; i ++)
114                ptr16[i] = (uint16_t)(i & 0xFFFF);
115
116        for (i = 0; i <  size / 2; i++) {
117                if (ptr16[i] != (uint16_t)(i & 0xFFFF))  {
118                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
119                                   (unsigned)(i & 0xFFFF), ptr16[i], (unsigned)(baseAddr + i));
120                        ret = 0;
121                }
122        }
123
124        if (!ret) return ret;
125
126        printf(" Test for DWORD accessing... \n\r");
127
128        /* Test for DWORD accessing */
129        for (i = 0; i < size / 4; i ++) {
130                ptr32[i] = (uint32_t)(i & 0xFFFFFFFF);
131                memory_barrier()
132        }
133
134        for (i = 0; i <  size / 4; i++) {
135                if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF))  {
136                        printf("-E- Expected:%x, read %x @ %x \n\r" ,
137                                   (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i));
138                        ret = 0;
139                }
140        }
141
142        return ret;
143}
144#endif /* __rtems__ */
145
146
147/**
148 * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access.
149 */
150
151
152void BOARD_ConfigureSdram(void)
153{
154#ifndef __rtems__
155        const Pin pinsSdram[] = {BOARD_SDRAM_PINS};
156#endif /* __rtems__ */
157        volatile uint32_t i;
158        volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR;
159
160        /* Configure PIO */
161#ifndef __rtems__
162        PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
163#endif /* __rtems__ */
164        PMC_EnablePeripheral(ID_SDRAMC);
165        MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN;
166
167        /* 1. SDRAM features must be set in the configuration register:
168        asynchronous timings (TRC, TRAS, etc.), number of columns, rows,
169        CAS latency, and the data bus width. */
170        SDRAMC->SDRAMC_CR =
171                SDRAMC_CR_NC_COL8      // 8 column bits
172                | SDRAMC_CR_NR_ROW11     // 12 row bits (4K)
173                | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3
174                | SDRAMC_CR_NB_BANK2     // 2 banks
175                | SDRAMC_CR_DBW          // 16 bit
176                | SDRAMC_CR_TWR(5)
177                | SDRAMC_CR_TRC_TRFC(13) // 63ns   min
178                | SDRAMC_CR_TRP(5)       // Command period (PRE to ACT) 21 ns min
179                | SDRAMC_CR_TRCD(
180                        5)      // Active Command to read/Write Command delay time 21ns min
181                | SDRAMC_CR_TRAS(9)      // Command period (ACT to PRE)  42ns min
182                | SDRAMC_CR_TXSR(15U);   // Exit self-refresh to active time  70ns Min
183
184        /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
185        strength (DS) and partial array self refresh (PASR) must be set in the
186        Low Power Register. */
187
188        /* 3. The SDRAM memory type must be set in the Memory Device Register.*/
189        SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
190
191        /* 4. A minimum pause of 200 ŠÌs is provided to precede any signal toggle.*/
192        for (i = 0; i < 100000; i++);
193
194        /* 5. (1)A NOP command is issued to the SDRAM devices. The application must
195        set Mode to 1 in the Mode Register and perform a write access to
196        any SDRAM address.*/
197        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
198        *pSdram = 0;
199
200        for (i = 0; i < 100000; i++);
201
202        /* 6. An All Banks Precharge command is issued to the SDRAM devices.
203        The application must set Mode to 2 in the Mode Register and perform a write
204        access to any SDRAM address. */
205        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
206        *pSdram = 0;
207
208        for (i = 0; i < 100000; i++);
209
210        /* 7. Eight auto-refresh (CBR) cycles are provided. The application must
211        set the Mode to 4 in the Mode Register and perform a write access to any
212        SDRAM location eight times.*/
213        for (i = 0; i < 8; i++) {
214                SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
215                *pSdram = 0;
216        }
217
218        for (i = 0; i < 100000; i++);
219
220        /*8. A Mode Register set (MRS) cycle is issued to program the parameters of
221        the SDRAM devices, in particular CAS latency and burst length. The
222        application must set Mode to 3 in the Mode Register and perform a write
223        access to the SDRAM. The write address must be chosen so that BA[1:0]
224        are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns,
225        4 banks) bank address, the SDRAM write access should be done at the address
226        0x70000000.*/
227        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
228        *pSdram = 0;
229
230        for (i = 0; i < 100000; i++);
231
232        /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS)
233        cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The
234        application must set Mode to 5 in the Mode Register and perform a write
235        access to the SDRAM. The write address must be chosen so that BA[1] or BA[0]
236        are set to 1.
237        For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank
238        address the SDRAM write access should be done at the address 0x70800000 or
239        0x70400000. */
240        //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
241        // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0;
242
243        /* 10. The application must go into Normal Mode, setting Mode to 0 in the
244        Mode Register and performing a write access at any location in the SDRAM. */
245        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
246        *pSdram = 0;
247
248        for (i = 0; i < 100000; i++);
249
250        /* 11. Write the refresh rate into the count field in the SDRAMC Refresh
251        Timer register. (Refresh rate = delay between refresh cycles).
252        The SDRAM device requires a refresh every 15.625 ŠÌs or 7.81 ŠÌs.
253        With a 100 MHz frequency, the Refresh Timer Counter Register must be set
254        with the value 1562(15.625 ŠÌs x 100 MHz) or 781(7.81 ŠÌs x 100 MHz). */
255        // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ŠÌs
256        /* ((32 x 10(^-3))/2048) x150 x (10^6) */
257        SDRAMC->SDRAMC_TR = 1562;
258        SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL;
259        /* After initialization, the SDRAM devices are fully functional. */
260}
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