[e1eeb883] | 1 | /* ---------------------------------------------------------------------------- */ |
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| 2 | /* Atmel Microcontroller Software Support */ |
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| 3 | /* SAM Software Package License */ |
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| 4 | /* ---------------------------------------------------------------------------- */ |
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| 5 | /* Copyright (c) 2015, Atmel Corporation */ |
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| 6 | /* */ |
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| 7 | /* All rights reserved. */ |
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| 8 | /* */ |
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| 9 | /* Redistribution and use in source and binary forms, with or without */ |
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| 10 | /* modification, are permitted provided that the following condition is met: */ |
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| 11 | /* */ |
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| 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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| 13 | /* this list of conditions and the disclaimer below. */ |
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| 14 | /* */ |
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| 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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| 16 | /* this software without specific prior written permission. */ |
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| 17 | /* */ |
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| 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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| 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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| 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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| 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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| 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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| 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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| 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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| 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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| 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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| 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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| 28 | /* ---------------------------------------------------------------------------- */ |
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| 29 | |
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| 30 | /** |
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| 31 | * \file |
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| 32 | * |
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| 33 | * Implementation of memories configuration on board. |
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| 34 | * |
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| 35 | */ |
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| 36 | |
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| 37 | /*---------------------------------------------------------------------------- |
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| 38 | * Headers |
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| 39 | *----------------------------------------------------------------------------*/ |
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[c354fac] | 40 | #ifndef __rtems__ |
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[e1eeb883] | 41 | #include "board.h" |
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[c354fac] | 42 | #else /* __rtems__ */ |
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| 43 | #include <chip.h> |
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| 44 | #include <include/board_memories.h> |
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| 45 | #endif /* __rtems__ */ |
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[e1eeb883] | 46 | |
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| 47 | /*---------------------------------------------------------------------------- |
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| 48 | * Exported functions |
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| 49 | *----------------------------------------------------------------------------*/ |
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| 50 | |
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| 51 | #define SDRAM_BA0 (1 << 20) |
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| 52 | #define SDRAM_BA1 (1 << 21) |
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| 53 | |
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| 54 | |
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[c354fac] | 55 | #ifndef __rtems__ |
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[e1eeb883] | 56 | uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size) |
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| 57 | { |
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| 58 | uint32_t i; |
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| 59 | uint32_t ret = 1; |
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| 60 | uint32_t *ptr32 = (uint32_t *) baseAddr; |
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| 61 | uint16_t *ptr16 = (uint16_t *) baseAddr; |
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| 62 | uint8_t *ptr8 = (uint8_t *) baseAddr; |
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| 63 | /* Test for 55AA55AA/AA55AA55 pattern */ |
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| 64 | printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r"); |
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| 65 | |
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| 66 | for (i = 0; i < size; i ++) { |
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| 67 | if (i & 1) |
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| 68 | ptr32[i] = 0x55AA55AA; |
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| 69 | else |
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| 70 | ptr32[i] = 0xAA55AA55; |
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| 71 | |
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| 72 | memory_barrier() |
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| 73 | } |
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| 74 | |
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| 75 | for (i = 0; i < size; i++) { |
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| 76 | if (i & 1) { |
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| 77 | if (ptr32[i] != 0x55AA55AA) { |
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| 78 | printf("-E- Expected:%x, read %x @ %x \n\r" , |
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| 79 | 0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i)); |
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| 80 | ret = 0; |
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| 81 | |
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| 82 | } |
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| 83 | } else { |
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| 84 | if (ptr32[i] != 0xAA55AA55) { |
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| 85 | printf("-E- Expected:%x, read %x @ %x \n\r" , |
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| 86 | 0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i)); |
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| 87 | ret = 0; |
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| 88 | } |
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| 89 | } |
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| 90 | } |
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| 91 | |
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| 92 | if (!ret) return ret; |
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| 93 | |
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| 94 | printf(" Test for BYTE accessing... \n\r"); |
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| 95 | |
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| 96 | /* Test for BYTE accessing */ |
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| 97 | for (i = 0; i < size; i ++) |
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| 98 | ptr8[i] = (uint8_t)(i & 0xFF); |
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| 99 | |
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| 100 | for (i = 0; i < size; i++) { |
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| 101 | if (ptr8[i] != (uint8_t)(i & 0xFF)) { |
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| 102 | printf("-E- Expected:%x, read %x @ %x \n\r" , |
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| 103 | (unsigned)(i & 0xFF), ptr8[i], (unsigned)(baseAddr + i)); |
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| 104 | ret = 0; |
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| 105 | } |
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| 106 | } |
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| 107 | |
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| 108 | if (!ret) return ret; |
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| 109 | |
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| 110 | printf(" Test for WORD accessing... \n\r"); |
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| 111 | |
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| 112 | /* Test for WORD accessing */ |
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| 113 | for (i = 0; i < size / 2; i ++) |
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| 114 | ptr16[i] = (uint16_t)(i & 0xFFFF); |
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| 115 | |
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| 116 | for (i = 0; i < size / 2; i++) { |
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| 117 | if (ptr16[i] != (uint16_t)(i & 0xFFFF)) { |
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| 118 | printf("-E- Expected:%x, read %x @ %x \n\r" , |
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| 119 | (unsigned)(i & 0xFFFF), ptr16[i], (unsigned)(baseAddr + i)); |
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| 120 | ret = 0; |
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| 121 | } |
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| 122 | } |
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| 123 | |
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| 124 | if (!ret) return ret; |
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| 125 | |
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| 126 | printf(" Test for DWORD accessing... \n\r"); |
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| 127 | |
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| 128 | /* Test for DWORD accessing */ |
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| 129 | for (i = 0; i < size / 4; i ++) { |
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| 130 | ptr32[i] = (uint32_t)(i & 0xFFFFFFFF); |
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| 131 | memory_barrier() |
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| 132 | } |
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| 133 | |
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| 134 | for (i = 0; i < size / 4; i++) { |
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| 135 | if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF)) { |
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| 136 | printf("-E- Expected:%x, read %x @ %x \n\r" , |
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| 137 | (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i)); |
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| 138 | ret = 0; |
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| 139 | } |
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| 140 | } |
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| 141 | |
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| 142 | return ret; |
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| 143 | } |
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[c354fac] | 144 | #endif /* __rtems__ */ |
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[e1eeb883] | 145 | |
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| 146 | |
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| 147 | /** |
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| 148 | * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access. |
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| 149 | */ |
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| 150 | |
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| 151 | |
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| 152 | void BOARD_ConfigureSdram(void) |
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| 153 | { |
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[c354fac] | 154 | #ifndef __rtems__ |
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[e1eeb883] | 155 | const Pin pinsSdram[] = {BOARD_SDRAM_PINS}; |
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[c354fac] | 156 | #endif /* __rtems__ */ |
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[e1eeb883] | 157 | volatile uint32_t i; |
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| 158 | volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR; |
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| 159 | |
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| 160 | /* Configure PIO */ |
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[c354fac] | 161 | #ifndef __rtems__ |
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[e1eeb883] | 162 | PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram)); |
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[c354fac] | 163 | #endif /* __rtems__ */ |
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[e1eeb883] | 164 | PMC_EnablePeripheral(ID_SDRAMC); |
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| 165 | MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; |
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| 166 | |
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| 167 | /* 1. SDRAM features must be set in the configuration register: |
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| 168 | asynchronous timings (TRC, TRAS, etc.), number of columns, rows, |
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| 169 | CAS latency, and the data bus width. */ |
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| 170 | SDRAMC->SDRAMC_CR = |
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| 171 | SDRAMC_CR_NC_COL8 // 8 column bits |
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| 172 | | SDRAMC_CR_NR_ROW11 // 12 row bits (4K) |
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| 173 | | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3 |
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| 174 | | SDRAMC_CR_NB_BANK2 // 2 banks |
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| 175 | | SDRAMC_CR_DBW // 16 bit |
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| 176 | | SDRAMC_CR_TWR(5) |
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| 177 | | SDRAMC_CR_TRC_TRFC(13) // 63ns min |
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| 178 | | SDRAMC_CR_TRP(5) // Command period (PRE to ACT) 21 ns min |
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| 179 | | SDRAMC_CR_TRCD( |
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| 180 | 5) // Active Command to read/Write Command delay time 21ns min |
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| 181 | | SDRAMC_CR_TRAS(9) // Command period (ACT to PRE) 42ns min |
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| 182 | | SDRAMC_CR_TXSR(15U); // Exit self-refresh to active time 70ns Min |
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| 183 | |
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| 184 | /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive |
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| 185 | strength (DS) and partial array self refresh (PASR) must be set in the |
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| 186 | Low Power Register. */ |
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| 187 | |
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| 188 | /* 3. The SDRAM memory type must be set in the Memory Device Register.*/ |
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| 189 | SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM; |
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| 190 | |
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| 191 | /* 4. A minimum pause of 200 ŠÌs is provided to precede any signal toggle.*/ |
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| 192 | for (i = 0; i < 100000; i++); |
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| 193 | |
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| 194 | /* 5. (1)A NOP command is issued to the SDRAM devices. The application must |
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| 195 | set Mode to 1 in the Mode Register and perform a write access to |
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| 196 | any SDRAM address.*/ |
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| 197 | SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP; |
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| 198 | *pSdram = 0; |
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| 199 | |
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| 200 | for (i = 0; i < 100000; i++); |
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| 201 | |
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| 202 | /* 6. An All Banks Precharge command is issued to the SDRAM devices. |
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| 203 | The application must set Mode to 2 in the Mode Register and perform a write |
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| 204 | access to any SDRAM address. */ |
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| 205 | SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE; |
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| 206 | *pSdram = 0; |
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| 207 | |
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| 208 | for (i = 0; i < 100000; i++); |
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| 209 | |
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| 210 | /* 7. Eight auto-refresh (CBR) cycles are provided. The application must |
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| 211 | set the Mode to 4 in the Mode Register and perform a write access to any |
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| 212 | SDRAM location eight times.*/ |
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| 213 | for (i = 0; i < 8; i++) { |
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| 214 | SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; |
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| 215 | *pSdram = 0; |
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| 216 | } |
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| 217 | |
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| 218 | for (i = 0; i < 100000; i++); |
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| 219 | |
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| 220 | /*8. A Mode Register set (MRS) cycle is issued to program the parameters of |
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| 221 | the SDRAM devices, in particular CAS latency and burst length. The |
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| 222 | application must set Mode to 3 in the Mode Register and perform a write |
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| 223 | access to the SDRAM. The write address must be chosen so that BA[1:0] |
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| 224 | are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, |
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| 225 | 4 banks) bank address, the SDRAM write access should be done at the address |
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| 226 | 0x70000000.*/ |
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| 227 | SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG; |
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| 228 | *pSdram = 0; |
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| 229 | |
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| 230 | for (i = 0; i < 100000; i++); |
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| 231 | |
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| 232 | /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) |
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| 233 | cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The |
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| 234 | application must set Mode to 5 in the Mode Register and perform a write |
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| 235 | access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] |
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| 236 | are set to 1. |
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| 237 | For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank |
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| 238 | address the SDRAM write access should be done at the address 0x70800000 or |
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| 239 | 0x70400000. */ |
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| 240 | //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG; |
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| 241 | // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0; |
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| 242 | |
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| 243 | /* 10. The application must go into Normal Mode, setting Mode to 0 in the |
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| 244 | Mode Register and performing a write access at any location in the SDRAM. */ |
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| 245 | SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL; |
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| 246 | *pSdram = 0; |
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| 247 | |
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| 248 | for (i = 0; i < 100000; i++); |
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| 249 | |
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| 250 | /* 11. Write the refresh rate into the count field in the SDRAMC Refresh |
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| 251 | Timer register. (Refresh rate = delay between refresh cycles). |
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| 252 | The SDRAM device requires a refresh every 15.625 ŠÌs or 7.81 ŠÌs. |
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| 253 | With a 100 MHz frequency, the Refresh Timer Counter Register must be set |
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| 254 | with the value 1562(15.625 ŠÌs x 100 MHz) or 781(7.81 ŠÌs x 100 MHz). */ |
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| 255 | // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ŠÌs |
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| 256 | /* ((32 x 10(^-3))/2048) x150 x (10^6) */ |
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| 257 | SDRAMC->SDRAMC_TR = 1562; |
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| 258 | SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL; |
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| 259 | /* After initialization, the SDRAM devices are fully functional. */ |
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| 260 | } |
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