source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c @ f7f420e

5
Last change on this file since f7f420e was f7f420e, checked in by Christian Mauderer <Christian.Mauderer@…>, on 09/06/17 at 05:42:06

bsp/atsam: Fix MPU sections.

The nocache section has been hard coded which could lead to problems
when a bigger region should be used. Fix that.

The internal SRAM has not been set up correctly. A duplicate external
SDRAM has been set up instead.

Remove a lot of other hard coded sections too.
  • Property mode set to 100644
File size: 14.1 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/**
31 * \file
32 *
33 * Provides the low-level initialization function that called on chip startup.
34 */
35
36/*----------------------------------------------------------------------------
37 *        Headers
38 *----------------------------------------------------------------------------*/
39
40#ifndef __rtems__
41#include "board.h"
42#else /* __rtems__ */
43#define MPU_HAS_NOCACHE_REGION
44#include <chip.h>
45#include <include/board_lowlevel.h>
46#endif /* __rtems__ */
47
48
49#if defined(ENABLE_TCM) && defined(__GNUC__)
50        extern char _itcm_lma, _sitcm, _eitcm;
51#endif
52
53
54/*----------------------------------------------------------------------------
55 *        Exported functions
56 *----------------------------------------------------------------------------*/
57/* Default memory map
58   NO. Address range          Memory region    Memory type     Shareable?    Cache policy
59   1   0x00000000- 0x1FFFFFFF Code             Normal
60       0x00000000- 0x003FFFFF ITCM
61       0x00400000- 0x005FFFFF Internal flash   Normal          Not shareable   WB
62   2   0x20000000- 0x3FFFFFFF SRAM             Normal
63       0x20000000- 0x203FFFFF DTCM
64       0x20400000- 0x2043FFFF First Partition  Normal          Not shareable   WB
65 if MPU_HAS_NOCACHE_REGION is defined
66       0x20440000- 0x2045EFFF Second Partition Normal          Not shareable   WB
67       0x2045F000- 0x2045FFFF Nocache SRAM     Normal          Shareable
68 if MPU_HAS_NOCACHE_REGION is NOT defined
69       0x20440000- 0x2045FFFF Second Partition Normal          Not shareable   WB
70   3   0x40000000- 0x5FFFFFFF Peripheral       Device          Shareable
71   4   0x60000000- 0x7FFFFFFF RAM
72       0x60000000- 0x6FFFFFFF External EBI  Strongly-ordered   Shareable
73       0x70000000- 0x7FFFFFFF SDRAM            Normal          Shareable       WBWA
74   5   0x80000000- 0x9FFFFFFF QSPI          Strongly-ordered   Shareable
75   6   0xA0100000- 0xA01FFFFF USBHS RAM        Device          Shareable
76   7   0xE0000000- 0xFFFFFFFF System           -                  -
77   */
78
79/**
80 * \brief Set up a memory region.
81 */
82void _SetupMemoryRegion(void)
83{
84
85        uint32_t dwRegionBaseAddr;
86        uint32_t dwRegionAttr;
87
88        memory_barrier();
89
90        /***************************************************
91            ITCM memory region --- Normal
92            START_Addr:-  0x00000000UL
93            END_Addr:-    0x003FFFFFUL
94        ****************************************************/
95
96        dwRegionBaseAddr =
97                ITCM_START_ADDRESS |
98                MPU_REGION_VALID |
99                MPU_DEFAULT_ITCM_REGION;        // 1
100
101#ifdef __rtems__
102        if (ITCM_END_ADDRESS + 1 != ITCM_START_ADDRESS) {
103#endif /* __rtems__ */
104        dwRegionAttr =
105                MPU_AP_PRIVILEGED_READ_WRITE |
106                MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
107                MPU_REGION_ENABLE;
108#ifdef __rtems__
109        } else {
110                dwRegionAttr = MPU_REGION_DISABLE;
111        }
112#endif /* __rtems__ */
113
114        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
115
116
117        /****************************************************
118            Internal flash memory region --- Normal read-only
119            (update to Strongly ordered in write accesses)
120            START_Addr:-  0x00400000UL
121            END_Addr:-    0x005FFFFFUL
122        ******************************************************/
123
124        dwRegionBaseAddr =
125                IFLASH_START_ADDRESS |
126                MPU_REGION_VALID |
127                MPU_DEFAULT_IFLASH_REGION;      //2
128
129        dwRegionAttr =
130                MPU_AP_READONLY |
131                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
132                MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
133                MPU_REGION_ENABLE;
134
135        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
136
137        /****************************************************
138            DTCM memory region --- Normal
139            START_Addr:-  0x20000000L
140            END_Addr:-    0x203FFFFFUL
141        ******************************************************/
142
143        /* DTCM memory region */
144        dwRegionBaseAddr =
145                DTCM_START_ADDRESS |
146                MPU_REGION_VALID |
147                MPU_DEFAULT_DTCM_REGION;         //3
148
149#ifdef __rtems__
150        if (DTCM_END_ADDRESS + 1 != DTCM_START_ADDRESS) {
151#endif /* __rtems__ */
152        dwRegionAttr =
153                MPU_AP_PRIVILEGED_READ_WRITE |
154                INNER_NORMAL_NOCACHE_TYPE(NON_SHAREABLE) |
155                MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
156                MPU_REGION_ENABLE;
157#ifdef __rtems__
158        } else {
159                dwRegionAttr = MPU_REGION_DISABLE;
160        }
161#endif /* __rtems__ */
162
163        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
164
165
166        /****************************************************
167            SRAM Cacheable memory region --- Normal
168            START_Addr:-  0x20400000UL
169            END_Addr:-    0x2043FFFFUL
170        ******************************************************/
171        /* SRAM memory  region */
172        dwRegionBaseAddr =
173                SRAM_FIRST_START_ADDRESS |
174                MPU_REGION_VALID |
175                MPU_DEFAULT_SRAM_REGION_1;         //4
176
177        dwRegionAttr =
178                MPU_AP_FULL_ACCESS    |
179                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
180                MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
181                | MPU_REGION_ENABLE;
182
183        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
184
185
186        /****************************************************
187            Internal SRAM second partition memory region --- Normal
188            START_Addr:-  0x20440000UL
189            END_Addr:-    0x2045FFFFUL
190        ******************************************************/
191#ifndef __rtems__
192        /* SRAM memory region */
193        dwRegionBaseAddr =
194                SRAM_SECOND_START_ADDRESS |
195                MPU_REGION_VALID |
196                MPU_DEFAULT_SRAM_REGION_2;         //5
197
198        dwRegionAttr =
199                MPU_AP_FULL_ACCESS    |
200                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
201                MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
202                MPU_REGION_ENABLE;
203
204        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
205#else /* __rtems__ */
206        /* NOTE: The first SRAM region is increased so it covers the whole SRAM. If
207         * the SRAM is something odd (like 384k on the SAME70Q21), the next higher
208         * power of two will be used (in the example: 512k). That removes the need of
209         * the second SRAM region. There is currently no memory after the SRAM so that
210         * shouldn't be a problem. */
211#endif /* __rtems__ */
212
213#ifdef MPU_HAS_NOCACHE_REGION
214        dwRegionBaseAddr =
215                SRAM_NOCACHE_START_ADDRESS |
216                MPU_REGION_VALID |
217                MPU_NOCACHE_SRAM_REGION;          //11
218
219        dwRegionAttr =
220                MPU_AP_FULL_ACCESS    |
221                INNER_OUTER_NORMAL_NOCACHE_TYPE(SHAREABLE) |
222                MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
223                MPU_REGION_ENABLE;
224
225        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
226#endif
227
228        /****************************************************
229            Peripheral memory region --- DEVICE Shareable
230            START_Addr:-  0x40000000UL
231            END_Addr:-    0x5FFFFFFFUL
232        ******************************************************/
233        dwRegionBaseAddr =
234                PERIPHERALS_START_ADDRESS |
235                MPU_REGION_VALID |
236                MPU_PERIPHERALS_REGION;          //6
237
238        dwRegionAttr = MPU_AP_FULL_ACCESS |
239                                   MPU_REGION_EXECUTE_NEVER |
240                                   SHAREABLE_DEVICE_TYPE |
241                                   MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
242                                   | MPU_REGION_ENABLE;
243
244        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
245
246#ifdef __rtems__
247        dwRegionBaseAddr =
248                SYSTEM_START_ADDRESS |
249                MPU_REGION_VALID |
250                MPU_SYSTEM_REGION;
251
252        dwRegionAttr = MPU_AP_FULL_ACCESS |
253                                   MPU_REGION_EXECUTE_NEVER |
254                                   SHAREABLE_DEVICE_TYPE |
255                                   MPU_CalMPURegionSize(SYSTEM_END_ADDRESS - SYSTEM_START_ADDRESS)
256                                   | MPU_REGION_ENABLE;
257
258        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
259#endif /* __rtems__ */
260
261        /****************************************************
262            External EBI memory  memory region --- Strongly Ordered
263            START_Addr:-  0x60000000UL
264            END_Addr:-    0x6FFFFFFFUL
265        ******************************************************/
266        dwRegionBaseAddr =
267                EXT_EBI_START_ADDRESS |
268                MPU_REGION_VALID |
269                MPU_EXT_EBI_REGION;
270
271        dwRegionAttr =
272                MPU_AP_FULL_ACCESS |
273                /* External memory Must be defined with 'Device' or 'Strongly Ordered'
274                attribute for write accesses (AXI) */
275                STRONGLY_ORDERED_SHAREABLE_TYPE |
276                MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
277                MPU_REGION_ENABLE;
278
279        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
280
281        /****************************************************
282            SDRAM Cacheable memory region --- Normal
283            START_Addr:-  0x70000000UL
284            END_Addr:-    0x7FFFFFFFUL
285        ******************************************************/
286        dwRegionBaseAddr =
287                SDRAM_START_ADDRESS |
288                MPU_REGION_VALID |
289                MPU_DEFAULT_SDRAM_REGION;        //7
290
291        dwRegionAttr =
292                MPU_AP_FULL_ACCESS    |
293                INNER_NORMAL_WB_RWA_TYPE(SHAREABLE) |
294                MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
295                MPU_REGION_ENABLE;
296
297        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
298
299        /****************************************************
300            QSPI memory region --- Normal
301            START_Addr:-  0x80000000UL
302            END_Addr:-    0x9FFFFFFFUL
303        ******************************************************/
304        dwRegionBaseAddr =
305                QSPI_START_ADDRESS |
306                MPU_REGION_VALID |
307                MPU_QSPIMEM_REGION;              //8
308
309#ifdef __rtems__
310        if (QSPI_END_ADDRESS + 1 != QSPI_START_ADDRESS) {
311#endif /* __rtems__ */
312        dwRegionAttr =
313                MPU_AP_FULL_ACCESS |
314                INNER_NORMAL_WB_NWA_TYPE(SHAREABLE) |
315                MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
316                MPU_REGION_ENABLE;
317#ifdef __rtems__
318        } else {
319                dwRegionAttr = MPU_REGION_DISABLE;
320        }
321#endif /* __rtems__ */
322
323        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
324
325
326        /****************************************************
327            USB RAM Memory region --- Device
328            START_Addr:-  0xA0100000UL
329            END_Addr:-    0xA01FFFFFUL
330        ******************************************************/
331        dwRegionBaseAddr =
332                USBHSRAM_START_ADDRESS |
333                MPU_REGION_VALID |
334                MPU_USBHSRAM_REGION;              //9
335
336        dwRegionAttr =
337                MPU_AP_FULL_ACCESS |
338                MPU_REGION_EXECUTE_NEVER |
339                SHAREABLE_DEVICE_TYPE |
340                MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
341                MPU_REGION_ENABLE;
342
343        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
344
345
346        /* Enable the memory management fault , Bus Fault, Usage Fault exception */
347        SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
348                                   | SCB_SHCSR_USGFAULTENA_Msk);
349
350        /* Enable the MPU region */
351#ifndef __rtems__
352        MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
353#else /* __rtems__ */
354        MPU_Enable(MPU_ENABLE);
355#endif /* __rtems__ */
356
357        memory_sync();
358}
359
360#ifdef ENABLE_TCM
361
362#if defined (__ICCARM__) /* IAR Ewarm */
363        #pragma section = "CSTACK"
364        #pragma section = "CSTACK_DTCM"
365        #define SRAM_STACK_BASE     (__section_begin("CSTACK"))
366        #define DTCM_STACK_BASE     (__section_begin("CSTACK_DTCM"))
367        #define SRAM_STACK_LIMIT    (__section_end("CSTACK"))
368        #define DTCM_STACK_LIMIT    (__section_end("CSTACK_DTCM"))
369#elif defined (__CC_ARM)  /* MDK */
370        extern uint32_t Image$$ARM_LIB_STACK$$Base;
371        extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
372        extern uint32_t Image$$DTCM_STACK$$Base;
373        extern uint32_t Image$$DTCM_STACK$$ZI$$Limit;
374        #define SRAM_STACK_BASE     (&Image$$ARM_LIB_STACK$$Base)
375        #define DTCM_STACK_BASE     (&Image$$DTCM_STACK$$Base)
376        #define SRAM_STACK_LIMIT    (&Image$$ARM_LIB_STACK$$ZI$$Limit)
377        #define DTCM_STACK_LIMIT    (&Image$$DTCM_STACK$$ZI$$Limit)
378#elif defined (__GNUC__)  /* GCC */
379        extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack;
380        #define SRAM_STACK_BASE     ((void *)(&_sstack))
381        #define DTCM_STACK_BASE     ((void *)(&_sdtcm_stack))
382        #define SRAM_STACK_LIMIT    ((void *)(&_estack))
383        #define DTCM_STACK_LIMIT    ((void *)(&_edtcm_stack))
384#endif
385
386/** \brief  Change stack's location to DTCM
387
388    The function changes the stack's location from SRAM to DTCM
389 */
390void TCM_StackInit(void);
391void TCM_StackInit(void)
392{
393        uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT;
394        volatile char *dst = (volatile char *)DTCM_STACK_LIMIT;
395        volatile char *src = (volatile char *)SRAM_STACK_LIMIT;
396
397        /* copy stack data from SRAM to DTCM */
398        while (src > (volatile char *)SRAM_STACK_BASE)
399                *--dst = *--src;
400
401        __set_MSP(__get_MSP() - offset);
402}
403
404#endif
405
406
407/**
408 * \brief Performs the low-level initialization of the chip.
409 */
410extern WEAK void LowLevelInit(void)
411{
412
413        SystemInit();
414#ifndef MPU_EXAMPLE_FEATURE
415        _SetupMemoryRegion();
416#endif
417
418#if defined(FFT_DEMO) && (defined(__GNUC__) || defined(__CC_ARM))
419        /* Enabling the FPU */
420        SCB->CPACR |= 0x00F00000;
421        __DSB();
422        __ISB();
423#endif
424
425#if defined(ENABLE_TCM) && defined(__GNUC__)
426        volatile char *dst = &_sitcm;
427        volatile char *src = &_itcm_lma;
428
429        /* copy code_TCM from flash to ITCM */
430        while (dst < &_eitcm)
431                *dst++ = *src++;
432
433#endif
434}
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