source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c @ c186de5c

5
Last change on this file since c186de5c was c186de5c, checked in by Alexander Krutwig <alexander.krutwig@…>, on 09/14/16 at 12:46:03

bsp/atsam: Use normal memory for QSPI flash area

This is a performance improvement for execute-in-place (XIP).
  • Property mode set to 100644
File size: 12.8 KB
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1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
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9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
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23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
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27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/**
31 * \file
32 *
33 * Provides the low-level initialization function that called on chip startup.
34 */
35
36/*----------------------------------------------------------------------------
37 *        Headers
38 *----------------------------------------------------------------------------*/
39
40#ifndef __rtems__
41#include "board.h"
42#else /* __rtems__ */
43#define MPU_HAS_NOCACHE_REGION
44#include <chip.h>
45#include <include/board_lowlevel.h>
46#endif /* __rtems__ */
47
48
49#if defined(ENABLE_TCM) && defined(__GNUC__)
50        extern char _itcm_lma, _sitcm, _eitcm;
51#endif
52
53
54/*----------------------------------------------------------------------------
55 *        Exported functions
56 *----------------------------------------------------------------------------*/
57/* Default memory map
58   NO. Address range          Memory region    Memory type     Shareable?    Cache policy
59   1   0x00000000- 0x1FFFFFFF Code             Normal
60       0x00000000- 0x003FFFFF ITCM
61       0x00400000- 0x005FFFFF Internal flash   Normal          Not shareable   WB
62   2   0x20000000- 0x3FFFFFFF SRAM             Normal
63       0x20000000- 0x203FFFFF DTCM
64       0x20400000- 0x2043FFFF First Partition  Normal          Not shareable   WB
65 if MPU_HAS_NOCACHE_REGION is defined
66       0x20440000- 0x2045EFFF Second Partition Normal          Not shareable   WB
67       0x2045F000- 0x2045FFFF Nocache SRAM     Normal          Shareable
68 if MPU_HAS_NOCACHE_REGION is NOT defined
69       0x20440000- 0x2045FFFF Second Partition Normal          Not shareable   WB
70   3   0x40000000- 0x5FFFFFFF Peripheral       Device          Shareable
71   4   0x60000000- 0x7FFFFFFF RAM
72       0x60000000- 0x6FFFFFFF External EBI  Strongly-ordered   Shareable
73       0x70000000- 0x7FFFFFFF SDRAM            Normal          Shareable       WBWA
74   5   0x80000000- 0x9FFFFFFF QSPI          Strongly-ordered   Shareable
75   6   0xA0100000- 0xA01FFFFF USBHS RAM        Device          Shareable
76   7   0xE0000000- 0xFFFFFFFF System           -                  -
77   */
78
79/**
80 * \brief Set up a memory region.
81 */
82void _SetupMemoryRegion(void)
83{
84
85        uint32_t dwRegionBaseAddr;
86        uint32_t dwRegionAttr;
87
88        memory_barrier();
89
90        /***************************************************
91            ITCM memory region --- Normal
92            START_Addr:-  0x00000000UL
93            END_Addr:-    0x003FFFFFUL
94        ****************************************************/
95        dwRegionBaseAddr =
96                ITCM_START_ADDRESS |
97                MPU_REGION_VALID |
98                MPU_DEFAULT_ITCM_REGION;        // 1
99
100        dwRegionAttr =
101                MPU_AP_PRIVILEGED_READ_WRITE |
102                MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
103                MPU_REGION_ENABLE;
104
105        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
106
107        /****************************************************
108            Internal flash memory region --- Normal read-only
109            (update to Strongly ordered in write accesses)
110            START_Addr:-  0x00400000UL
111            END_Addr:-    0x005FFFFFUL
112        ******************************************************/
113
114        dwRegionBaseAddr =
115                IFLASH_START_ADDRESS |
116                MPU_REGION_VALID |
117                MPU_DEFAULT_IFLASH_REGION;      //2
118
119        dwRegionAttr =
120                MPU_AP_READONLY |
121                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
122                MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
123                MPU_REGION_ENABLE;
124
125        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
126
127        /****************************************************
128            DTCM memory region --- Normal
129            START_Addr:-  0x20000000L
130            END_Addr:-    0x203FFFFFUL
131        ******************************************************/
132
133        /* DTCM memory region */
134        dwRegionBaseAddr =
135                DTCM_START_ADDRESS |
136                MPU_REGION_VALID |
137                MPU_DEFAULT_DTCM_REGION;         //3
138
139        dwRegionAttr =
140                MPU_AP_PRIVILEGED_READ_WRITE |
141                INNER_NORMAL_NOCACHE_TYPE(NON_SHAREABLE) |
142                MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
143                MPU_REGION_ENABLE;
144
145        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
146
147        /****************************************************
148            SRAM Cacheable memory region --- Normal
149            START_Addr:-  0x20400000UL
150            END_Addr:-    0x2043FFFFUL
151        ******************************************************/
152        /* SRAM memory  region */
153        dwRegionBaseAddr =
154                SRAM_FIRST_START_ADDRESS |
155                MPU_REGION_VALID |
156                MPU_DEFAULT_SRAM_REGION_1;         //4
157
158        dwRegionAttr =
159                MPU_AP_FULL_ACCESS    |
160                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
161                MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
162                | MPU_REGION_ENABLE;
163
164        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
165
166
167        /****************************************************
168            Internal SRAM second partition memory region --- Normal
169            START_Addr:-  0x20440000UL
170            END_Addr:-    0x2045FFFFUL
171        ******************************************************/
172#ifndef __rtems__
173        /* SRAM memory region */
174        dwRegionBaseAddr =
175                SRAM_SECOND_START_ADDRESS |
176                MPU_REGION_VALID |
177                MPU_DEFAULT_SRAM_REGION_2;         //5
178
179        dwRegionAttr =
180                MPU_AP_FULL_ACCESS    |
181                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
182                MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
183                MPU_REGION_ENABLE;
184
185        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
186#endif /* __rtems__ */
187
188#ifdef MPU_HAS_NOCACHE_REGION
189        dwRegionBaseAddr =
190                SRAM_NOCACHE_START_ADDRESS |
191                MPU_REGION_VALID |
192                MPU_NOCACHE_SRAM_REGION;          //11
193
194        dwRegionAttr =
195                MPU_AP_FULL_ACCESS    |
196                INNER_OUTER_NORMAL_NOCACHE_TYPE(SHAREABLE) |
197                MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
198                MPU_REGION_ENABLE;
199
200        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
201#endif
202
203        /****************************************************
204            Peripheral memory region --- DEVICE Shareable
205            START_Addr:-  0x40000000UL
206            END_Addr:-    0x5FFFFFFFUL
207        ******************************************************/
208        dwRegionBaseAddr =
209                PERIPHERALS_START_ADDRESS |
210                MPU_REGION_VALID |
211                MPU_PERIPHERALS_REGION;          //6
212
213        dwRegionAttr = MPU_AP_FULL_ACCESS |
214                                   MPU_REGION_EXECUTE_NEVER |
215                                   SHAREABLE_DEVICE_TYPE |
216                                   MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
217                                   | MPU_REGION_ENABLE;
218
219        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
220
221
222        /****************************************************
223            External EBI memory  memory region --- Strongly Ordered
224            START_Addr:-  0x60000000UL
225            END_Addr:-    0x6FFFFFFFUL
226        ******************************************************/
227        dwRegionBaseAddr =
228                EXT_EBI_START_ADDRESS |
229                MPU_REGION_VALID |
230                MPU_EXT_EBI_REGION;
231
232        dwRegionAttr =
233                MPU_AP_FULL_ACCESS |
234                /* External memory Must be defined with 'Device' or 'Strongly Ordered'
235                attribute for write accesses (AXI) */
236                STRONGLY_ORDERED_SHAREABLE_TYPE |
237                MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
238                MPU_REGION_ENABLE;
239
240        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
241
242        /****************************************************
243            SDRAM Cacheable memory region --- Normal
244            START_Addr:-  0x70000000UL
245            END_Addr:-    0x7FFFFFFFUL
246        ******************************************************/
247        dwRegionBaseAddr =
248                SDRAM_START_ADDRESS |
249                MPU_REGION_VALID |
250                MPU_DEFAULT_SDRAM_REGION;        //7
251
252        dwRegionAttr =
253                MPU_AP_FULL_ACCESS    |
254                INNER_NORMAL_WB_RWA_TYPE(SHAREABLE) |
255                MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
256                MPU_REGION_ENABLE;
257
258        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
259
260        /****************************************************
261            QSPI memory region --- Normal
262            START_Addr:-  0x80000000UL
263            END_Addr:-    0x9FFFFFFFUL
264        ******************************************************/
265        dwRegionBaseAddr =
266                QSPI_START_ADDRESS |
267                MPU_REGION_VALID |
268                MPU_QSPIMEM_REGION;              //8
269
270        dwRegionAttr =
271                MPU_AP_FULL_ACCESS |
272                INNER_NORMAL_WB_NWA_TYPE(SHAREABLE) |
273                MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
274                MPU_REGION_ENABLE;
275
276        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
277
278
279        /****************************************************
280            USB RAM Memory region --- Device
281            START_Addr:-  0xA0100000UL
282            END_Addr:-    0xA01FFFFFUL
283        ******************************************************/
284        dwRegionBaseAddr =
285                USBHSRAM_START_ADDRESS |
286                MPU_REGION_VALID |
287                MPU_USBHSRAM_REGION;              //9
288
289        dwRegionAttr =
290                MPU_AP_FULL_ACCESS |
291                MPU_REGION_EXECUTE_NEVER |
292                SHAREABLE_DEVICE_TYPE |
293                MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
294                MPU_REGION_ENABLE;
295
296        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
297
298
299        /* Enable the memory management fault , Bus Fault, Usage Fault exception */
300        SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
301                                   | SCB_SHCSR_USGFAULTENA_Msk);
302
303        /* Enable the MPU region */
304        MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
305
306        memory_sync();
307}
308
309#ifdef ENABLE_TCM
310
311#if defined (__ICCARM__) /* IAR Ewarm */
312        #pragma section = "CSTACK"
313        #pragma section = "CSTACK_DTCM"
314        #define SRAM_STACK_BASE     (__section_begin("CSTACK"))
315        #define DTCM_STACK_BASE     (__section_begin("CSTACK_DTCM"))
316        #define SRAM_STACK_LIMIT    (__section_end("CSTACK"))
317        #define DTCM_STACK_LIMIT    (__section_end("CSTACK_DTCM"))
318#elif defined (__CC_ARM)  /* MDK */
319        extern uint32_t Image$$ARM_LIB_STACK$$Base;
320        extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
321        extern uint32_t Image$$DTCM_STACK$$Base;
322        extern uint32_t Image$$DTCM_STACK$$ZI$$Limit;
323        #define SRAM_STACK_BASE     (&Image$$ARM_LIB_STACK$$Base)
324        #define DTCM_STACK_BASE     (&Image$$DTCM_STACK$$Base)
325        #define SRAM_STACK_LIMIT    (&Image$$ARM_LIB_STACK$$ZI$$Limit)
326        #define DTCM_STACK_LIMIT    (&Image$$DTCM_STACK$$ZI$$Limit)
327#elif defined (__GNUC__)  /* GCC */
328        extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack;
329        #define SRAM_STACK_BASE     ((void *)(&_sstack))
330        #define DTCM_STACK_BASE     ((void *)(&_sdtcm_stack))
331        #define SRAM_STACK_LIMIT    ((void *)(&_estack))
332        #define DTCM_STACK_LIMIT    ((void *)(&_edtcm_stack))
333#endif
334
335/** \brief  Change stack's location to DTCM
336
337    The function changes the stack's location from SRAM to DTCM
338 */
339void TCM_StackInit(void);
340void TCM_StackInit(void)
341{
342        uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT;
343        volatile char *dst = (volatile char *)DTCM_STACK_LIMIT;
344        volatile char *src = (volatile char *)SRAM_STACK_LIMIT;
345
346        /* copy stack data from SRAM to DTCM */
347        while (src > (volatile char *)SRAM_STACK_BASE)
348                *--dst = *--src;
349
350        __set_MSP(__get_MSP() - offset);
351}
352
353#endif
354
355
356/**
357 * \brief Performs the low-level initialization of the chip.
358 */
359extern WEAK void LowLevelInit(void)
360{
361
362        SystemInit();
363#ifndef MPU_EXAMPLE_FEATURE
364        _SetupMemoryRegion();
365#endif
366
367#if defined(FFT_DEMO) && (defined(__GNUC__) || defined(__CC_ARM))
368        /* Enabling the FPU */
369        SCB->CPACR |= 0x00F00000;
370        __DSB();
371        __ISB();
372#endif
373
374#if defined(ENABLE_TCM) && defined(__GNUC__)
375        volatile char *dst = &_sitcm;
376        volatile char *src = &_itcm_lma;
377
378        /* copy code_TCM from flash to ITCM */
379        while (dst < &_eitcm)
380                *dst++ = *src++;
381
382#endif
383}
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