source: rtems/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c @ 9bb3ce39

5
Last change on this file since 9bb3ce39 was 0bd49f1, checked in by Sebastian Huber <sebastian.huber@…>, on 03/22/16 at 07:34:16

bsp/atsam: Add nocache region support
  • Property mode set to 100644
File size: 12.7 KB
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1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/**
31 * \file
32 *
33 * Provides the low-level initialization function that called on chip startup.
34 */
35
36/*----------------------------------------------------------------------------
37 *        Headers
38 *----------------------------------------------------------------------------*/
39
40#ifndef __rtems__
41#include "board.h"
42#else /* __rtems__ */
43#define MPU_HAS_NOCACHE_REGION
44#include <chip.h>
45#include <include/board_lowlevel.h>
46#endif /* __rtems__ */
47
48
49#if defined(ENABLE_TCM) && defined(__GNUC__)
50        extern char _itcm_lma, _sitcm, _eitcm;
51#endif
52
53
54/*----------------------------------------------------------------------------
55 *        Exported functions
56 *----------------------------------------------------------------------------*/
57/* Default memory map
58   NO. Address range          Memory region    Memory type     Shareable?    Cache policy
59   1   0x00000000- 0x1FFFFFFF Code             Normal
60       0x00000000- 0x003FFFFF ITCM
61       0x00400000- 0x005FFFFF Internal flash   Normal          Not shareable   WB
62   2   0x20000000- 0x3FFFFFFF SRAM             Normal
63       0x20000000- 0x203FFFFF DTCM
64       0x20400000- 0x2043FFFF First Partition  Normal          Not shareable   WB
65 if MPU_HAS_NOCACHE_REGION is defined
66       0x20440000- 0x2045EFFF Second Partition Normal          Not shareable   WB
67       0x2045F000- 0x2045FFFF Nocache SRAM     Normal          Shareable
68 if MPU_HAS_NOCACHE_REGION is NOT defined
69       0x20440000- 0x2045FFFF Second Partition Normal          Not shareable   WB
70   3   0x40000000- 0x5FFFFFFF Peripheral       Device          Shareable
71   4   0x60000000- 0x7FFFFFFF RAM
72       0x60000000- 0x6FFFFFFF External EBI  Strongly-ordered   Shareable
73       0x70000000- 0x7FFFFFFF SDRAM            Normal          Shareable       WBWA
74   5   0x80000000- 0x9FFFFFFF QSPI          Strongly-ordered   Shareable
75   6   0xA0100000- 0xA01FFFFF USBHS RAM        Device          Shareable
76   7   0xE0000000- 0xFFFFFFFF System           -                  -
77   */
78
79/**
80 * \brief Set up a memory region.
81 */
82void _SetupMemoryRegion(void)
83{
84
85        uint32_t dwRegionBaseAddr;
86        uint32_t dwRegionAttr;
87
88        memory_barrier();
89
90        /***************************************************
91            ITCM memory region --- Normal
92            START_Addr:-  0x00000000UL
93            END_Addr:-    0x003FFFFFUL
94        ****************************************************/
95        dwRegionBaseAddr =
96                ITCM_START_ADDRESS |
97                MPU_REGION_VALID |
98                MPU_DEFAULT_ITCM_REGION;        // 1
99
100        dwRegionAttr =
101                MPU_AP_PRIVILEGED_READ_WRITE |
102                MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
103                MPU_REGION_ENABLE;
104
105        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
106
107        /****************************************************
108            Internal flash memory region --- Normal read-only
109            (update to Strongly ordered in write accesses)
110            START_Addr:-  0x00400000UL
111            END_Addr:-    0x005FFFFFUL
112        ******************************************************/
113
114        dwRegionBaseAddr =
115                IFLASH_START_ADDRESS |
116                MPU_REGION_VALID |
117                MPU_DEFAULT_IFLASH_REGION;      //2
118
119        dwRegionAttr =
120                MPU_AP_READONLY |
121                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
122                MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
123                MPU_REGION_ENABLE;
124
125        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
126
127        /****************************************************
128            DTCM memory region --- Normal
129            START_Addr:-  0x20000000L
130            END_Addr:-    0x203FFFFFUL
131        ******************************************************/
132
133        /* DTCM memory region */
134        dwRegionBaseAddr =
135                DTCM_START_ADDRESS |
136                MPU_REGION_VALID |
137                MPU_DEFAULT_DTCM_REGION;         //3
138
139        dwRegionAttr =
140                MPU_AP_PRIVILEGED_READ_WRITE |
141                MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
142                MPU_REGION_ENABLE;
143
144        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
145
146        /****************************************************
147            SRAM Cacheable memory region --- Normal
148            START_Addr:-  0x20400000UL
149            END_Addr:-    0x2043FFFFUL
150        ******************************************************/
151        /* SRAM memory  region */
152        dwRegionBaseAddr =
153                SRAM_FIRST_START_ADDRESS |
154                MPU_REGION_VALID |
155                MPU_DEFAULT_SRAM_REGION_1;         //4
156
157        dwRegionAttr =
158                MPU_AP_FULL_ACCESS    |
159                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
160                MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
161                | MPU_REGION_ENABLE;
162
163        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
164
165
166        /****************************************************
167            Internal SRAM second partition memory region --- Normal
168            START_Addr:-  0x20440000UL
169            END_Addr:-    0x2045FFFFUL
170        ******************************************************/
171        /* SRAM memory region */
172        dwRegionBaseAddr =
173                SRAM_SECOND_START_ADDRESS |
174                MPU_REGION_VALID |
175                MPU_DEFAULT_SRAM_REGION_2;         //5
176
177        dwRegionAttr =
178                MPU_AP_FULL_ACCESS    |
179                INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
180                MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
181                MPU_REGION_ENABLE;
182
183        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
184
185#ifdef MPU_HAS_NOCACHE_REGION
186        dwRegionBaseAddr =
187                SRAM_NOCACHE_START_ADDRESS |
188                MPU_REGION_VALID |
189                MPU_NOCACHE_SRAM_REGION;          //11
190
191        dwRegionAttr =
192                MPU_AP_FULL_ACCESS    |
193                INNER_OUTER_NORMAL_NOCACHE_TYPE(SHAREABLE) |
194                MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
195                MPU_REGION_ENABLE;
196
197        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
198#endif
199
200        /****************************************************
201            Peripheral memory region --- DEVICE Shareable
202            START_Addr:-  0x40000000UL
203            END_Addr:-    0x5FFFFFFFUL
204        ******************************************************/
205        dwRegionBaseAddr =
206                PERIPHERALS_START_ADDRESS |
207                MPU_REGION_VALID |
208                MPU_PERIPHERALS_REGION;          //6
209
210        dwRegionAttr = MPU_AP_FULL_ACCESS |
211                                   MPU_REGION_EXECUTE_NEVER |
212                                   SHAREABLE_DEVICE_TYPE |
213                                   MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
214                                   | MPU_REGION_ENABLE;
215
216        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
217
218
219        /****************************************************
220            External EBI memory  memory region --- Strongly Ordered
221            START_Addr:-  0x60000000UL
222            END_Addr:-    0x6FFFFFFFUL
223        ******************************************************/
224        dwRegionBaseAddr =
225                EXT_EBI_START_ADDRESS |
226                MPU_REGION_VALID |
227                MPU_EXT_EBI_REGION;
228
229        dwRegionAttr =
230                MPU_AP_FULL_ACCESS |
231                /* External memory Must be defined with 'Device' or 'Strongly Ordered'
232                attribute for write accesses (AXI) */
233                STRONGLY_ORDERED_SHAREABLE_TYPE |
234                MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
235                MPU_REGION_ENABLE;
236
237        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
238
239        /****************************************************
240            SDRAM Cacheable memory region --- Normal
241            START_Addr:-  0x70000000UL
242            END_Addr:-    0x7FFFFFFFUL
243        ******************************************************/
244        dwRegionBaseAddr =
245                SDRAM_START_ADDRESS |
246                MPU_REGION_VALID |
247                MPU_DEFAULT_SDRAM_REGION;        //7
248
249        dwRegionAttr =
250                MPU_AP_FULL_ACCESS    |
251                INNER_NORMAL_WB_RWA_TYPE(SHAREABLE) |
252                MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
253                MPU_REGION_ENABLE;
254
255        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
256
257        /****************************************************
258            QSPI memory region --- Strongly ordered
259            START_Addr:-  0x80000000UL
260            END_Addr:-    0x9FFFFFFFUL
261        ******************************************************/
262        dwRegionBaseAddr =
263                QSPI_START_ADDRESS |
264                MPU_REGION_VALID |
265                MPU_QSPIMEM_REGION;              //8
266
267        dwRegionAttr =
268                MPU_AP_FULL_ACCESS |
269                STRONGLY_ORDERED_SHAREABLE_TYPE |
270                MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
271                MPU_REGION_ENABLE;
272
273        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
274
275
276        /****************************************************
277            USB RAM Memory region --- Device
278            START_Addr:-  0xA0100000UL
279            END_Addr:-    0xA01FFFFFUL
280        ******************************************************/
281        dwRegionBaseAddr =
282                USBHSRAM_START_ADDRESS |
283                MPU_REGION_VALID |
284                MPU_USBHSRAM_REGION;              //9
285
286        dwRegionAttr =
287                MPU_AP_FULL_ACCESS |
288                MPU_REGION_EXECUTE_NEVER |
289                SHAREABLE_DEVICE_TYPE |
290                MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
291                MPU_REGION_ENABLE;
292
293        MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
294
295
296        /* Enable the memory management fault , Bus Fault, Usage Fault exception */
297        SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
298                                   | SCB_SHCSR_USGFAULTENA_Msk);
299
300        /* Enable the MPU region */
301        MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
302
303        memory_sync();
304}
305
306#ifdef ENABLE_TCM
307
308#if defined (__ICCARM__) /* IAR Ewarm */
309        #pragma section = "CSTACK"
310        #pragma section = "CSTACK_DTCM"
311        #define SRAM_STACK_BASE     (__section_begin("CSTACK"))
312        #define DTCM_STACK_BASE     (__section_begin("CSTACK_DTCM"))
313        #define SRAM_STACK_LIMIT    (__section_end("CSTACK"))
314        #define DTCM_STACK_LIMIT    (__section_end("CSTACK_DTCM"))
315#elif defined (__CC_ARM)  /* MDK */
316        extern uint32_t Image$$ARM_LIB_STACK$$Base;
317        extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
318        extern uint32_t Image$$DTCM_STACK$$Base;
319        extern uint32_t Image$$DTCM_STACK$$ZI$$Limit;
320        #define SRAM_STACK_BASE     (&Image$$ARM_LIB_STACK$$Base)
321        #define DTCM_STACK_BASE     (&Image$$DTCM_STACK$$Base)
322        #define SRAM_STACK_LIMIT    (&Image$$ARM_LIB_STACK$$ZI$$Limit)
323        #define DTCM_STACK_LIMIT    (&Image$$DTCM_STACK$$ZI$$Limit)
324#elif defined (__GNUC__)  /* GCC */
325        extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack;
326        #define SRAM_STACK_BASE     ((void *)(&_sstack))
327        #define DTCM_STACK_BASE     ((void *)(&_sdtcm_stack))
328        #define SRAM_STACK_LIMIT    ((void *)(&_estack))
329        #define DTCM_STACK_LIMIT    ((void *)(&_edtcm_stack))
330#endif
331
332/** \brief  Change stack's location to DTCM
333
334    The function changes the stack's location from SRAM to DTCM
335 */
336void TCM_StackInit(void);
337void TCM_StackInit(void)
338{
339        uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT;
340        volatile char *dst = (volatile char *)DTCM_STACK_LIMIT;
341        volatile char *src = (volatile char *)SRAM_STACK_LIMIT;
342
343        /* copy stack data from SRAM to DTCM */
344        while (src > (volatile char *)SRAM_STACK_BASE)
345                *--dst = *--src;
346
347        __set_MSP(__get_MSP() - offset);
348}
349
350#endif
351
352
353/**
354 * \brief Performs the low-level initialization of the chip.
355 */
356extern WEAK void LowLevelInit(void)
357{
358
359        SystemInit();
360#ifndef MPU_EXAMPLE_FEATURE
361        _SetupMemoryRegion();
362#endif
363
364#if defined(FFT_DEMO) && (defined(__GNUC__) || defined(__CC_ARM))
365        /* Enabling the FPU */
366        SCB->CPACR |= 0x00F00000;
367        __DSB();
368        __ISB();
369#endif
370
371#if defined(ENABLE_TCM) && defined(__GNUC__)
372        volatile char *dst = &_sitcm;
373        volatile char *src = &_itcm_lma;
374
375        /* copy code_TCM from flash to ITCM */
376        while (dst < &_eitcm)
377                *dst++ = *src++;
378
379#endif
380}
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