[e1eeb883] | 1 | /* ---------------------------------------------------------------------------- */ |
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| 2 | /* Atmel Microcontroller Software Support */ |
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| 3 | /* SAM Software Package License */ |
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| 4 | /* ---------------------------------------------------------------------------- */ |
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| 5 | /* Copyright (c) 2015, Atmel Corporation */ |
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| 6 | /* */ |
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| 7 | /* All rights reserved. */ |
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| 8 | /* */ |
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| 9 | /* Redistribution and use in source and binary forms, with or without */ |
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| 10 | /* modification, are permitted provided that the following condition is met: */ |
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| 11 | /* */ |
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| 12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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| 13 | /* this list of conditions and the disclaimer below. */ |
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| 14 | /* */ |
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| 15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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| 16 | /* this software without specific prior written permission. */ |
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| 17 | /* */ |
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| 18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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| 19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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| 20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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| 21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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| 22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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| 23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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| 24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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| 25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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| 26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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| 27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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| 28 | /* ---------------------------------------------------------------------------- */ |
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| 29 | |
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| 30 | #include "samv71.h" |
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| 31 | |
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| 32 | /* @cond 0 */ |
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| 33 | /**INDENT-OFF**/ |
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| 34 | #ifdef __cplusplus |
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| 35 | extern "C" { |
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| 36 | #endif |
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| 37 | /**INDENT-ON**/ |
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| 38 | /* @endcond */ |
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| 39 | |
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| 40 | /* %ATMEL_SYSTEM% */ |
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| 41 | /* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */ |
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| 42 | /* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */ |
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| 43 | #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) |
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| 44 | #ifdef MCK_123MHZ |
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| 45 | /* For example usb_video, PLLA/HCLK/MCK clock is set to 492/246/123MHz to achieve |
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| 46 | the maximum performance, for other examples the clock is set to 300/300/150MHz */ |
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| 47 | #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x28U) | \ |
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| 48 | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)) |
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| 49 | |
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| 50 | #define SYS_BOARD_MCKR_MDIV (PMC_MCKR_MDIV_PCK_DIV2) |
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| 51 | #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK \ |
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| 52 | | SYS_BOARD_MCKR_MDIV) |
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| 53 | #else |
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| 54 | #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) | \ |
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| 55 | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)) |
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| 56 | |
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| 57 | #define SYS_BOARD_MCKR_MDIV (PMC_MCKR_MDIV_PCK_DIV2) |
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| 58 | #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK \ |
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| 59 | | SYS_BOARD_MCKR_MDIV) |
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| 60 | #endif |
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| 61 | |
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| 62 | uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; |
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| 63 | #define USBCLK_DIV 10 |
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| 64 | |
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| 65 | /** |
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| 66 | * \brief Setup the microcontroller system. |
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| 67 | * Initialize the System and update the SystemFrequency variable. |
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| 68 | */ |
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| 69 | void SystemInit(void) |
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| 70 | { |
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| 71 | uint32_t read_MOR; |
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| 72 | /* Set FWS according to SYS_BOARD_MCKR configuration */ |
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| 73 | EFC->EEFC_FMR = EEFC_FMR_FWS(5); |
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| 74 | |
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| 75 | /* Before switching MAIN OSC on external crystal : enable it and don't |
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| 76 | * disable at the same time RC OSC in case of if MAIN OSC is still using RC |
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| 77 | * OSC |
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| 78 | */ |
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| 79 | |
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| 80 | read_MOR = PMC->CKGR_MOR; |
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| 81 | /* enable external crystal - enable RC OSC */ |
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| 82 | read_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME); |
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| 83 | PMC->CKGR_MOR = read_MOR; |
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| 84 | |
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| 85 | /* Select XTAL 32k instead of internal slow RC 32k for slow clock */ |
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| 86 | if ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST) { |
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| 87 | SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; |
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| 88 | |
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| 89 | while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)); |
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| 90 | } |
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| 91 | |
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| 92 | /* Initialize main oscillator */ |
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| 93 | if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) { |
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| 94 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | |
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| 95 | CKGR_MOR_MOSCXTEN; |
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| 96 | |
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| 97 | while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { |
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| 98 | } |
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| 99 | } |
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| 100 | |
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| 101 | /* Switch to 3-20MHz Xtal oscillator */ |
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| 102 | PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | |
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| 103 | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; |
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| 104 | |
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| 105 | while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { |
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| 106 | } |
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| 107 | |
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| 108 | PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | |
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| 109 | PMC_MCKR_CSS_MAIN_CLK; |
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| 110 | |
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| 111 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { |
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| 112 | } |
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| 113 | |
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| 114 | /* Initialize PLLA */ |
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| 115 | PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; |
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| 116 | |
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| 117 | while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { |
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| 118 | } |
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| 119 | |
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| 120 | /* Switch to main clock: DO NOT modify MDIV and CSS feild at the same access */ |
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| 121 | PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_MDIV_Msk) | |
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| 122 | SYS_BOARD_MCKR_MDIV; |
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| 123 | PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; |
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| 124 | |
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| 125 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { |
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| 126 | } |
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| 127 | |
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| 128 | /* Switch to PLLA */ |
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| 129 | PMC->PMC_MCKR = SYS_BOARD_MCKR; |
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| 130 | |
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| 131 | while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { |
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| 132 | } |
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| 133 | |
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| 134 | SystemCoreClock = CHIP_FREQ_CPU_MAX; |
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| 135 | } |
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| 136 | |
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| 137 | void SystemCoreClockUpdate(void) |
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| 138 | { |
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| 139 | /* Determine clock frequency according to clock register values */ |
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| 140 | switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) { |
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| 141 | case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ |
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| 142 | if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) |
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| 143 | SystemCoreClock = CHIP_FREQ_XTAL_32K; |
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| 144 | else |
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| 145 | SystemCoreClock = CHIP_FREQ_SLCK_RC; |
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| 146 | |
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| 147 | break; |
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| 148 | |
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| 149 | case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ |
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| 150 | if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) |
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| 151 | SystemCoreClock = CHIP_FREQ_XTAL_12M; |
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| 152 | else { |
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| 153 | SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; |
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| 154 | |
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| 155 | switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { |
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| 156 | case CKGR_MOR_MOSCRCF_4_MHz: |
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| 157 | break; |
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| 158 | |
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| 159 | case CKGR_MOR_MOSCRCF_8_MHz: |
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| 160 | SystemCoreClock *= 2U; |
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| 161 | break; |
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| 162 | |
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| 163 | case CKGR_MOR_MOSCRCF_12_MHz: |
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| 164 | SystemCoreClock *= 3U; |
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| 165 | break; |
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| 166 | |
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| 167 | default: |
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| 168 | break; |
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| 169 | } |
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| 170 | } |
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| 171 | |
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| 172 | break; |
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| 173 | |
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| 174 | case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ |
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| 175 | if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) |
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| 176 | SystemCoreClock = CHIP_FREQ_XTAL_12M; |
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| 177 | else { |
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| 178 | SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; |
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| 179 | |
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| 180 | switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) { |
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| 181 | case CKGR_MOR_MOSCRCF_4_MHz: |
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| 182 | break; |
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| 183 | |
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| 184 | case CKGR_MOR_MOSCRCF_8_MHz: |
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| 185 | SystemCoreClock *= 2U; |
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| 186 | break; |
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| 187 | |
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| 188 | case CKGR_MOR_MOSCRCF_12_MHz: |
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| 189 | SystemCoreClock *= 3U; |
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| 190 | break; |
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| 191 | |
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| 192 | default: |
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| 193 | break; |
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| 194 | } |
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| 195 | } |
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| 196 | |
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| 197 | if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == |
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| 198 | PMC_MCKR_CSS_PLLA_CLK) { |
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| 199 | SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> |
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| 200 | CKGR_PLLAR_MULA_Pos) + 1U); |
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| 201 | SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> |
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| 202 | CKGR_PLLAR_DIVA_Pos)); |
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| 203 | } |
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| 204 | |
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| 205 | break; |
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| 206 | |
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| 207 | default: |
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| 208 | break; |
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| 209 | } |
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| 210 | |
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| 211 | if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) |
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| 212 | SystemCoreClock /= 3U; |
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| 213 | else |
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| 214 | SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); |
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| 215 | } |
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| 216 | /** |
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| 217 | * Initialize flash. |
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| 218 | */ |
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| 219 | void system_init_flash(uint32_t ul_clk) |
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| 220 | { |
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| 221 | /* Set FWS for embedded Flash access according to operating frequency */ |
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| 222 | if (ul_clk < CHIP_FREQ_FWS_0) |
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| 223 | EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; |
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| 224 | else { |
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| 225 | if (ul_clk < CHIP_FREQ_FWS_1) |
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| 226 | EFC->EEFC_FMR = EEFC_FMR_FWS(1) | EEFC_FMR_CLOE; |
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| 227 | else { |
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| 228 | if (ul_clk < CHIP_FREQ_FWS_2) |
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| 229 | EFC->EEFC_FMR = EEFC_FMR_FWS(2) | EEFC_FMR_CLOE; |
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| 230 | else { |
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| 231 | if (ul_clk < CHIP_FREQ_FWS_3) |
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| 232 | EFC->EEFC_FMR = EEFC_FMR_FWS(3) | EEFC_FMR_CLOE; |
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| 233 | else { |
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| 234 | if (ul_clk < CHIP_FREQ_FWS_4) |
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| 235 | EFC->EEFC_FMR = EEFC_FMR_FWS(4) | EEFC_FMR_CLOE; |
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| 236 | else |
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| 237 | EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; |
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| 238 | } |
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| 239 | } |
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| 240 | } |
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| 241 | } |
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| 242 | } |
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| 243 | |
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| 244 | /** |
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| 245 | * \brief Enable USB clock. |
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| 246 | * |
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| 247 | * \param pll_id Source of the USB clock. |
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| 248 | * \param div Actual clock divisor. Must be superior to 0. |
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| 249 | */ |
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| 250 | void sysclk_enable_usb(void) |
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| 251 | { |
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| 252 | /* Disable FS USB clock*/ |
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| 253 | PMC->PMC_SCDR = PMC_SCDR_USBCLK; |
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| 254 | |
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| 255 | /* Enable PLL 480 MHz */ |
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| 256 | PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF); |
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| 257 | |
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| 258 | /* Wait that PLL is considered locked by the PMC */ |
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| 259 | while (!(PMC->PMC_SR & PMC_SR_LOCKU)); |
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| 260 | |
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| 261 | /* USB clock register: USB Clock Input is UTMI PLL */ |
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| 262 | PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1)); |
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| 263 | |
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| 264 | PMC->PMC_SCER = PMC_SCER_USBCLK; |
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| 265 | } |
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| 266 | |
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| 267 | |
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| 268 | /** |
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| 269 | * \brief Disables USB clock. |
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| 270 | * |
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| 271 | * |
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| 272 | * \param pll_id Source of the USB clock. |
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| 273 | * \param div Actual clock divisor. Must be superior to 0. |
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| 274 | */ |
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| 275 | void sysclk_disable_usb(void) |
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| 276 | { |
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| 277 | /* Disable FS USB clock*/ |
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| 278 | PMC->PMC_SCDR = PMC_SCDR_USBCLK; |
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| 279 | |
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| 280 | /* Enable PLL 480 MHz */ |
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| 281 | PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF); |
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| 282 | |
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| 283 | /* Wait that PLL is considered locked by the PMC */ |
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| 284 | while (!(PMC->PMC_SR & PMC_SR_LOCKU)); |
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| 285 | |
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| 286 | /* USB clock register: USB Clock Input is UTMI PLL */ |
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| 287 | PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1)); |
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| 288 | } |
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| 289 | |
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| 290 | /* @cond 0 */ |
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| 291 | /**INDENT-OFF**/ |
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| 292 | #ifdef __cplusplus |
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| 293 | } |
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| 294 | #endif |
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| 295 | /**INDENT-ON**/ |
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| 296 | /* @endcond */ |
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