1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/atsam-clock-config.h> |
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16 | #include <bsp/atsam-i2c.h> |
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17 | |
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18 | #include <rtems/irq-extension.h> |
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19 | |
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20 | #define ATSAMV_I2C_IRQ_ERROR \ |
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21 | (TWIHS_IDR_ARBLST \ |
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22 | | TWIHS_IDR_TOUT \ |
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23 | | TWIHS_IDR_OVRE \ |
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24 | | TWIHS_IDR_UNRE \ |
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25 | | TWIHS_IDR_NACK) |
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26 | |
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27 | #define TEN_BIT_MASK 0xFC00 |
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28 | #define SEVEN_BIT_MASK 0xFF80 |
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29 | #define TEN_BIT_START_ADDR_MASK 0x78 |
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30 | #define LAST_TWO_BITS_MASK 0x03 |
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31 | #define LAST_BYTE_MASK 0x00FF |
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32 | |
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33 | static void |
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34 | atsam_i2c_disable_interrupts(Twihs *regs) |
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35 | { |
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36 | regs->TWIHS_IDR = 0xFFFFFFFF; |
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37 | } |
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38 | |
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39 | static void |
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40 | atsam_i2c_set_transfer_status(transfer_desc *trans_desc, transfer_state state) |
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41 | { |
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42 | trans_desc->trans_state = state; |
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43 | } |
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44 | |
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45 | static void |
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46 | atsam_i2c_continue_read(Twihs *regs, transfer_desc *trans_desc) |
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47 | { |
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48 | trans_desc->data[trans_desc->already_transferred] = TWI_ReadByte(regs); |
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49 | trans_desc->already_transferred++; |
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50 | |
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51 | /* check for transfer finish */ |
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52 | if (trans_desc->already_transferred == trans_desc->data_size) { |
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53 | if (trans_desc->stop_request){ |
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54 | TWI_DisableIt(regs, TWIHS_IDR_RXRDY); |
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55 | TWI_EnableIt(regs, TWIHS_IER_TXCOMP); |
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56 | atsam_i2c_set_transfer_status(trans_desc, TX_RX_STOP_SENT); |
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57 | } else { |
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58 | atsam_i2c_set_transfer_status(trans_desc, RX_CONT_MESSAGE_NEEDED); |
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59 | } |
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60 | } |
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61 | /* Last byte? */ |
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62 | else if ((trans_desc->already_transferred == (trans_desc->data_size - 1)) |
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63 | && (trans_desc->stop_request)){ |
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64 | TWI_Stop(regs); |
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65 | } |
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66 | } |
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67 | |
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68 | static bool |
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69 | atsam_i2c_is_state(transfer_desc *trans_desc, transfer_state state) |
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70 | { |
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71 | return (trans_desc->trans_state == state); |
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72 | } |
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73 | |
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74 | static void |
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75 | atsam_i2c_continue_write(Twihs *regs, transfer_desc *trans_desc) |
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76 | { |
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77 | /* Transfer finished ? */ |
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78 | if (trans_desc->already_transferred == trans_desc->data_size) { |
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79 | TWI_DisableIt(regs, TWIHS_IDR_TXRDY); |
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80 | if (trans_desc->stop_request){ |
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81 | TWI_EnableIt(regs, TWIHS_IER_TXCOMP); |
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82 | TWI_SendSTOPCondition(regs); |
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83 | atsam_i2c_set_transfer_status(trans_desc, TX_RX_STOP_SENT); |
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84 | } else { |
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85 | atsam_i2c_set_transfer_status(trans_desc, TX_CONT_MESSAGE_NEEDED); |
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86 | } |
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87 | } |
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88 | /* Bytes remaining */ |
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89 | else { |
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90 | TWI_WriteByte(regs, |
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91 | trans_desc->data[trans_desc->already_transferred]); |
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92 | trans_desc->already_transferred++; |
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93 | } |
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94 | } |
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95 | |
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96 | static void |
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97 | atsam_i2c_finish_write_transfer(Twihs *regs, transfer_desc *trans_desc) |
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98 | { |
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99 | TWI_ReadByte(regs); |
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100 | TWI_DisableIt(regs, TWIHS_IDR_TXCOMP); |
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101 | trans_desc->status = 0; |
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102 | } |
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103 | |
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104 | static void |
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105 | atsam_i2c_next_packet(atsam_i2c_bus *bus) |
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106 | { |
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107 | i2c_msg *msg; |
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108 | |
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109 | ++bus->msgs; |
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110 | --bus->msg_todo; |
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111 | |
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112 | msg = &bus->msgs[0]; |
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113 | |
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114 | bus->current_msg_todo = msg->len; |
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115 | bus->current_msg_byte = msg->buf; |
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116 | } |
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117 | |
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118 | static void |
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119 | atsam_i2c_set_td(atsam_i2c_bus *bus, uint32_t already_transferred, |
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120 | bool stop_needed) |
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121 | { |
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122 | transfer_desc *trans_desc = &bus->trans_desc; |
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123 | |
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124 | trans_desc->status = ASYNC_STATUS_PENDING; |
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125 | trans_desc->data = bus->current_msg_byte; |
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126 | trans_desc->data_size = bus->current_msg_todo; |
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127 | trans_desc->already_transferred = already_transferred; |
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128 | trans_desc->stop_request = stop_needed; |
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129 | } |
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130 | |
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131 | static bool |
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132 | atsam_i2c_set_address_size(const i2c_msg *msg) |
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133 | { |
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134 | bool rv = ((msg->flags & I2C_M_TEN) == 0) ? false : true; |
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135 | return rv; |
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136 | } |
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137 | |
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138 | static void |
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139 | atsam_i2c_set_address_regs(Twihs *regs, uint16_t address, bool ten_bit_addr, |
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140 | bool read_transfer) |
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141 | { |
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142 | /* No internal addresses used */ |
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143 | uint32_t mmr_temp = 0; |
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144 | uint32_t iadr_temp = 0; |
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145 | |
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146 | assert(regs != NULL); |
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147 | if (ten_bit_addr){ |
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148 | uint8_t addr_temp = TEN_BIT_START_ADDR_MASK; |
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149 | assert(address & TEN_BIT_MASK); |
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150 | mmr_temp = (1u << 8) | ((addr_temp & LAST_TWO_BITS_MASK) << 16); |
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151 | iadr_temp = (addr_temp & LAST_BYTE_MASK); |
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152 | } else { |
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153 | assert((address & SEVEN_BIT_MASK) == 0); |
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154 | mmr_temp = (address << 16); |
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155 | } |
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156 | |
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157 | if (read_transfer){ |
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158 | mmr_temp |= TWIHS_MMR_MREAD; |
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159 | } |
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160 | |
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161 | /* Set slave and number of internal address bytes */ |
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162 | regs->TWIHS_MMR = 0; |
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163 | regs->TWIHS_MMR = mmr_temp; |
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164 | |
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165 | /* Set internal address bytes */ |
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166 | regs->TWIHS_IADR = 0; |
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167 | regs->TWIHS_IADR = iadr_temp; |
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168 | } |
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169 | |
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170 | static void |
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171 | atsam_i2c_setup_read_transfer(Twihs *regs, bool ctrl, uint16_t slave_addr, |
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172 | bool send_stop) |
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173 | { |
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174 | TWI_EnableIt(regs, TWIHS_IER_RXRDY); |
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175 | atsam_i2c_set_address_regs(regs, slave_addr, ctrl, true); |
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176 | if (send_stop){ |
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177 | regs->TWIHS_CR = TWIHS_CR_START | TWIHS_CR_STOP; |
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178 | } else { |
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179 | regs->TWIHS_CR = TWIHS_CR_START; |
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180 | } |
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181 | } |
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182 | |
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183 | static void |
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184 | atsam_i2c_setup_write_transfer(atsam_i2c_bus *bus, Twihs *regs, bool ctrl, |
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185 | uint16_t slave_addr) |
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186 | { |
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187 | atsam_i2c_set_address_regs(regs, slave_addr, ctrl, false); |
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188 | TWI_WriteByte(regs, *bus->current_msg_byte); |
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189 | TWI_EnableIt(regs, TWIHS_IER_TXRDY); |
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190 | } |
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191 | |
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192 | static void |
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193 | atsam_i2c_setup_transfer(atsam_i2c_bus *bus, Twihs *regs) |
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194 | { |
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195 | const i2c_msg *msgs = bus->msgs; |
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196 | bool send_stop = false; |
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197 | uint32_t msg_todo = bus->msg_todo; |
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198 | uint16_t slave_addr; |
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199 | bool ten_bit_addr = false; |
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200 | uint32_t already_transferred; |
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201 | bool stop_needed = true; |
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202 | |
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203 | ten_bit_addr = atsam_i2c_set_address_size(msgs); |
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204 | |
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205 | if ((msg_todo > 1) && ((msgs[1].flags & I2C_M_NOSTART) != 0)){ |
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206 | stop_needed = false; |
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207 | } |
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208 | |
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209 | bus->read = (msgs->flags & I2C_M_RD) != 0; |
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210 | slave_addr = msgs->addr; |
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211 | already_transferred = (bus->read == true) ? 0 : 1; |
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212 | atsam_i2c_set_td(bus, already_transferred, stop_needed); |
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213 | |
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214 | transfer_desc *trans_desc = &bus->trans_desc; |
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215 | |
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216 | if (bus->read){ |
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217 | if (bus->current_msg_todo == 1){ |
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218 | send_stop = true; |
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219 | } |
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220 | atsam_i2c_set_transfer_status(trans_desc, RX_SEND_DATA); |
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221 | atsam_i2c_setup_read_transfer(regs, ten_bit_addr, |
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222 | slave_addr, send_stop); |
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223 | } else { |
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224 | atsam_i2c_set_transfer_status(trans_desc, TX_SEND_DATA); |
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225 | atsam_i2c_setup_write_transfer(bus, regs, ten_bit_addr, |
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226 | slave_addr); |
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227 | } |
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228 | } |
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229 | |
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230 | static void |
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231 | atsam_i2c_interrupt(void *arg) |
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232 | { |
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233 | atsam_i2c_bus *bus = arg; |
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234 | uint32_t irqstatus; |
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235 | bool done = false; |
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236 | transfer_desc *trans_desc; |
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237 | |
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238 | Twihs *regs = bus->regs; |
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239 | |
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240 | /* read interrupts */ |
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241 | irqstatus = regs->TWIHS_SR; |
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242 | |
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243 | if((irqstatus & (TWIHS_SR_ARBLST | TWIHS_SR_NACK)) != 0) { |
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244 | done = true; |
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245 | } |
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246 | |
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247 | trans_desc = &bus->trans_desc; |
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248 | |
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249 | if (((irqstatus & TWIHS_SR_RXRDY) != 0) && |
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250 | (atsam_i2c_is_state(trans_desc, RX_SEND_DATA))){ |
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251 | /* carry on read transfer */ |
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252 | atsam_i2c_continue_read(regs, trans_desc); |
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253 | } else if (((irqstatus & TWIHS_SR_TXCOMP) != 0) && |
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254 | (atsam_i2c_is_state(trans_desc, TX_RX_STOP_SENT))){ |
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255 | atsam_i2c_finish_write_transfer(regs, trans_desc); |
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256 | done = true; |
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257 | } else if (((irqstatus & TWIHS_SR_TXRDY) != 0) && |
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258 | (atsam_i2c_is_state(trans_desc, TX_SEND_DATA))){ |
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259 | atsam_i2c_continue_write(regs, trans_desc); |
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260 | if (trans_desc->trans_state == TX_CONT_MESSAGE_NEEDED){ |
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261 | done = true; |
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262 | } |
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263 | } |
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264 | |
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265 | if(done){ |
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266 | uint32_t err = irqstatus & ATSAMV_I2C_IRQ_ERROR; |
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267 | |
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268 | atsam_i2c_next_packet(bus); |
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269 | if (bus->msg_todo == 0 || err != 0) { |
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270 | rtems_status_code sc; |
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271 | |
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272 | atsam_i2c_disable_interrupts(regs); |
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273 | sc = rtems_event_transient_send(bus->task_id); |
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274 | assert(sc == RTEMS_SUCCESSFUL); |
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275 | } else { |
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276 | atsam_i2c_setup_transfer(bus, regs); |
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277 | } |
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278 | } |
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279 | } |
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280 | |
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281 | static int |
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282 | atsam_i2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t msg_count) |
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283 | { |
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284 | rtems_status_code sc; |
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285 | atsam_i2c_bus *bus = (atsam_i2c_bus *)base; |
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286 | Twihs *regs; |
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287 | uint32_t i; |
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288 | |
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289 | rtems_task_wake_after(1); |
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290 | |
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291 | if (msg_count < 1){ |
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292 | return 1; |
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293 | } |
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294 | |
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295 | for (i = 0; i < msg_count; ++i) { |
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296 | if ((msgs[i].flags & I2C_M_RECV_LEN) != 0) { |
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297 | return -EINVAL; |
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298 | } |
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299 | } |
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300 | |
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301 | bus->msgs = &msgs[0]; |
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302 | bus->msg_todo = msg_count; |
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303 | bus->current_msg_todo = msgs[0].len; |
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304 | bus->current_msg_byte = msgs[0].buf; |
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305 | bus->task_id = rtems_task_self(); |
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306 | |
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307 | regs = bus->regs; |
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308 | |
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309 | atsam_i2c_setup_transfer(bus, regs); |
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310 | |
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311 | regs->TWIHS_IER = ATSAMV_I2C_IRQ_ERROR; |
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312 | |
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313 | sc = rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout); |
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314 | if (sc != RTEMS_SUCCESSFUL){ |
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315 | rtems_event_transient_clear(); |
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316 | return -ETIMEDOUT; |
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317 | } |
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318 | |
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319 | return 0; |
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320 | } |
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321 | |
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322 | static int |
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323 | atsam_i2c_set_clock(i2c_bus *base, unsigned long clock) |
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324 | { |
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325 | atsam_i2c_bus *bus = (atsam_i2c_bus *)base; |
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326 | Twihs *regs = bus->regs; |
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327 | TWI_ConfigureMaster(regs, clock, BOARD_MCK); |
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328 | return 0; |
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329 | } |
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330 | |
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331 | static void |
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332 | atsam_i2c_destroy(i2c_bus *base) |
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333 | { |
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334 | atsam_i2c_bus *bus = (atsam_i2c_bus *)base; |
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335 | rtems_status_code sc; |
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336 | |
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337 | sc = rtems_interrupt_handler_remove(bus->irq, atsam_i2c_interrupt, bus); |
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338 | assert(sc == RTEMS_SUCCESSFUL); |
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339 | |
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340 | i2c_bus_destroy_and_free(&bus->base); |
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341 | } |
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342 | |
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343 | static void |
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344 | atsam_i2c_init(atsam_i2c_bus *bus, uint32_t input_clock, Twihs *board_base, |
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345 | uint32_t board_id, const Pin *pins) |
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346 | { |
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347 | |
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348 | /* Initialize the TWI */ |
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349 | PIO_Configure(pins, TWI_AMOUNT_PINS); |
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350 | |
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351 | /* Enable the TWI clock */ |
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352 | ENABLE_PERIPHERAL(board_id); |
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353 | |
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354 | TWI_ConfigureMaster(board_base, input_clock, BOARD_MCK); |
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355 | } |
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356 | |
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357 | int |
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358 | i2c_bus_register_atsam( |
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359 | const char *bus_path, |
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360 | Twihs *register_base, |
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361 | rtems_vector_number irq, |
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362 | const Pin pins[TWI_AMOUNT_PINS] |
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363 | ) |
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364 | { |
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365 | atsam_i2c_bus *bus; |
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366 | rtems_status_code sc; |
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367 | uint32_t board_id = (uint32_t) irq; |
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368 | |
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369 | bus = (atsam_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus)); |
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370 | if (bus == NULL){ |
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371 | return -1; |
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372 | } |
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373 | |
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374 | bus->regs = register_base; |
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375 | bus->irq = irq; |
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376 | |
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377 | atsam_i2c_init(bus, I2C_BUS_CLOCK_DEFAULT, bus->regs, |
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378 | board_id, pins); |
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379 | |
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380 | sc = rtems_interrupt_handler_install( |
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381 | irq, |
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382 | "Atsamv_I2C", |
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383 | RTEMS_INTERRUPT_UNIQUE, |
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384 | atsam_i2c_interrupt, |
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385 | bus |
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386 | ); |
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387 | if(sc != RTEMS_SUCCESSFUL){ |
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388 | (*bus->base.destroy)(&bus->base); |
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389 | |
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390 | rtems_set_errno_and_return_minus_one(EIO); |
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391 | } |
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392 | |
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393 | bus->base.transfer = atsam_i2c_transfer; |
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394 | bus->base.set_clock = atsam_i2c_set_clock; |
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395 | bus->base.destroy = atsam_i2c_destroy; |
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396 | |
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397 | return i2c_bus_register(&bus->base, bus_path); |
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398 | } |
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