1 | AC_PREREQ([2.69]) |
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2 | AC_INIT([rtems-c-src-lib-libbsp-arm-atsam],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) |
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3 | AC_CONFIG_SRCDIR([make/custom/atsamv.cfg]) |
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4 | RTEMS_TOP(../../../../../..) |
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5 | RTEMS_SOURCE_TOP |
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6 | RTEMS_BUILD_TOP |
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7 | RTEMS_BSP_LINKCMDS |
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8 | |
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9 | RTEMS_CANONICAL_TARGET_CPU |
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10 | AM_INIT_AUTOMAKE([no-define nostdinc foreign subdir-objects 1.12.2]) |
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11 | RTEMS_BSP_CONFIGURE |
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12 | |
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13 | |
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14 | |
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15 | RTEMS_BSP_CLEANUP_OPTIONS |
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16 | AC_ARG_ENABLE( |
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17 | [chip], |
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18 | [AS_HELP_STRING([--enable-chip],[select a chip variant (default samv71q21)])], |
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19 | [case "${enableval}" in |
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20 | same70j19) AC_DEFINE([__SAME70J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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21 | same70j20) AC_DEFINE([__SAME70J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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22 | same70j21) AC_DEFINE([__SAME70J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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23 | same70n19) AC_DEFINE([__SAME70N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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24 | same70n20) AC_DEFINE([__SAME70N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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25 | same70n21) AC_DEFINE([__SAME70N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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26 | same70q19) AC_DEFINE([__SAME70Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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27 | same70q20) AC_DEFINE([__SAME70Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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28 | same70q21) AC_DEFINE([__SAME70Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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29 | sams70j19) AC_DEFINE([__SAMS70J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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30 | sams70j20) AC_DEFINE([__SAMS70J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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31 | sams70j21) AC_DEFINE([__SAMS70J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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32 | sams70n19) AC_DEFINE([__SAMS70N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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33 | sams70n20) AC_DEFINE([__SAMS70N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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34 | sams70n21) AC_DEFINE([__SAMS70N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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35 | sams70q19) AC_DEFINE([__SAMS70Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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36 | sams70q20) AC_DEFINE([__SAMS70Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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37 | sams70q21) AC_DEFINE([__SAMS70Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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38 | samv71j19) AC_DEFINE([__SAMV71J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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39 | samv71j20) AC_DEFINE([__SAMV71J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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40 | samv71j21) AC_DEFINE([__SAMV71J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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41 | samv71n19) AC_DEFINE([__SAMV71N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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42 | samv71n20) AC_DEFINE([__SAMV71N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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43 | samv71n21) AC_DEFINE([__SAMV71N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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44 | samv71q19) AC_DEFINE([__SAMV71Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;; |
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45 | samv71q20) AC_DEFINE([__SAMV71Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;; |
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46 | samv71q21) AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;; |
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47 | *) AC_MSG_ERROR([bad value ${enableval} for chip variant]) ;; |
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48 | esac], |
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49 | [AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000]) |
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50 | |
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51 | AC_ARG_ENABLE( |
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52 | [sdram], |
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53 | [AS_HELP_STRING([--enable-sdram],[select a SDRAM variant (default is42s16100e-7bli)])], |
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54 | [case "${enableval}" in |
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55 | is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;; |
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56 | is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;; |
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57 | mt48lc16m16a2p-6a) AC_DEFINE([ATSAM_SDRAM_MT48LC16M16A2P_6A],[1],[SDRAM variant]) EXTSDRAM=0x02000000 ;; |
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58 | *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;; |
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59 | esac], |
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60 | [AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000]) |
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61 | |
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62 | RTEMS_BSPOPTS_SET([BOARD_MAINOSC],[*],[12000000]) |
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63 | RTEMS_BSPOPTS_HELP([BOARD_MAINOSC],[Main oscillator frequency in Hz (default 12MHz)]) |
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64 | |
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65 | RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[123000000]) |
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66 | RTEMS_BSPOPTS_HELP([ATSAM_MCK], |
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67 | [Frequency of the MCK in Hz. Set to 0 to force application defined speed. |
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68 | See startup/pmc-config.c for available clock configurations.]) |
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69 | |
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70 | RTEMS_BSPOPTS_SET([ATSAM_SLOWCLOCK_USE_XTAL],[*],[1]) |
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71 | RTEMS_BSPOPTS_HELP([ATSAM_SLOWCLOCK_USE_XTAL], |
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72 | [Use the external crystal as source for the slow clock instead of the internal |
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73 | RC oscillator. Note that on the ATSAM the NRST pin seems to depend on the slow |
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74 | clock as well as all watchdogs. If ATSAM_SLOWCLOCK_USE_XTAL is set to 1 without |
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75 | a external crystal connected, the controller might hang in the switching process |
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76 | without a working NRST pin. ]) |
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77 | |
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78 | RTEMS_BSPOPTS_SET([ATSAM_CHANGE_CLOCK_FROM_SRAM],[*],[0]) |
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79 | RTEMS_BSPOPTS_HELP([ATSAM_CHANGE_CLOCK_FROM_SRAM], |
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80 | [Move the functions that set up the clock into the SRAM. |
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81 | This allows to change the clock frequency even if the application is started from SDRAM. |
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82 | Requires a TCM_SIZE > 0.]) |
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83 | |
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84 | RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_BAUD],[*],[115200]) |
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85 | RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_BAUD],[initial baud for console devices (default 115200)]) |
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86 | |
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87 | RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_DEVICE_TYPE],[*],[0]) |
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88 | RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_DEVICE_TYPE],[device type for /dev/console, use 0 for USART and 1 for UART (default USART)]) |
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89 | |
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90 | RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_DEVICE_INDEX],[*],[1]) |
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91 | RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_DEVICE_INDEX],[device index for /dev/console (default 1, e.g. USART1)]) |
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92 | |
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93 | RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_USE_INTERRUPTS],[*],[1]) |
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94 | RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)]) |
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95 | |
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96 | AC_DEFUN([ATSAM_LINKCMD],[ |
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97 | AC_ARG_VAR([$1],[$2])dnl |
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98 | [$1]=[$]{[$1]:-[$3]} |
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99 | ]) |
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100 | |
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101 | ATSAM_LINKCMD([ATSAM_MEMORY_TCM_SIZE],[size of tightly coupled memories (TCM) in bytes],[0x00000000]) |
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102 | ATSAM_LINKCMD([ATSAM_MEMORY_INTFLASH_SIZE],[size of internal flash in bytes],[${INTFLASH}]) |
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103 | ATSAM_LINKCMD([ATSAM_MEMORY_INTSRAM_SIZE],[size of internal SRAM in bytes],[${INTSRAM}]) |
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104 | ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[${EXTSDRAM}]) |
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105 | ATSAM_LINKCMD([ATSAM_MEMORY_QSPIFLASH_SIZE],[size of QSPI flash in bytes],[0x00200000]) |
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106 | ATSAM_LINKCMD([ATSAM_MEMORY_NOCACHE_SIZE],[size of NOCACHE section in bytes],[0x00001000]) |
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107 | |
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108 | AC_CONFIG_FILES([ |
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109 | Makefile |
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110 | linkcmds.memory:startup/linkcmds.memory.in |
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111 | ]) |
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112 | AC_OUTPUT |
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