source: rtems/c/src/lib/libbsp/arm/atsam/configure.ac

Last change on this file was 37dc047, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 21, 2018 at 8:00:43 AM

bsps: Remove AC_CONFIG_SRCDIR()

This AC_CONFIG_SRCDIR() is just a sanity check in this insane build
system. Since all content of
c/src/lib/libbsp/@RTEMS_CPU@/@RTEMS_BSP_FAMILY@ is bound to be moved it
makes no sense to keep it.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 6.4 KB
Line 
1AC_PREREQ([2.69])
2AC_INIT([rtems-c-src-lib-libbsp-arm-atsam],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
3RTEMS_TOP(../../../../../..)
4RTEMS_SOURCE_TOP
5RTEMS_BUILD_TOP
6RTEMS_BSP_LINKCMDS
7
8RTEMS_CANONICAL_TARGET_CPU
9AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
10RTEMS_BSP_CONFIGURE
11
12
13
14RTEMS_BSP_CLEANUP_OPTIONS
15AC_ARG_ENABLE(
16[chip],
17[AS_HELP_STRING([--enable-chip],[select a chip variant (default samv71q21)])],
18[case "${enableval}" in
19  same70j19) AC_DEFINE([__SAME70J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
20  same70j20) AC_DEFINE([__SAME70J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
21  same70j21) AC_DEFINE([__SAME70J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
22  same70n19) AC_DEFINE([__SAME70N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
23  same70n20) AC_DEFINE([__SAME70N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
24  same70n21) AC_DEFINE([__SAME70N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
25  same70q19) AC_DEFINE([__SAME70Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
26  same70q20) AC_DEFINE([__SAME70Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
27  same70q21) AC_DEFINE([__SAME70Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
28  sams70j19) AC_DEFINE([__SAMS70J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
29  sams70j20) AC_DEFINE([__SAMS70J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
30  sams70j21) AC_DEFINE([__SAMS70J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
31  sams70n19) AC_DEFINE([__SAMS70N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
32  sams70n20) AC_DEFINE([__SAMS70N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
33  sams70n21) AC_DEFINE([__SAMS70N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
34  sams70q19) AC_DEFINE([__SAMS70Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
35  sams70q20) AC_DEFINE([__SAMS70Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
36  sams70q21) AC_DEFINE([__SAMS70Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
37  samv71j19) AC_DEFINE([__SAMV71J19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
38  samv71j20) AC_DEFINE([__SAMV71J20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
39  samv71j21) AC_DEFINE([__SAMV71J21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
40  samv71n19) AC_DEFINE([__SAMV71N19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
41  samv71n20) AC_DEFINE([__SAMV71N20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
42  samv71n21) AC_DEFINE([__SAMV71N21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
43  samv71q19) AC_DEFINE([__SAMV71Q19__],[1],[chip variant]) INTFLASH=0x00080000 ; INTSRAM=0x00040000 ;;
44  samv71q20) AC_DEFINE([__SAMV71Q20__],[1],[chip variant]) INTFLASH=0x00100000 ; INTSRAM=0x00060000 ;;
45  samv71q21) AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000 ;;
46  *) AC_MSG_ERROR([bad value ${enableval} for chip variant]) ;;
47esac],
48[AC_DEFINE([__SAMV71Q21__],[1],[chip variant]) INTFLASH=0x00200000 ; INTSRAM=0x00060000])
49
50AC_ARG_ENABLE(
51[sdram],
52[AS_HELP_STRING([--enable-sdram],[select a SDRAM variant (default is42s16100e-7bli)])],
53[case "${enableval}" in
54  is42s16100e-7bli) AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000 ;;
55  is42s16320f-7bl) AC_DEFINE([ATSAM_SDRAM_IS42S16320F_7BL],[1],[SDRAM variant]) EXTSDRAM=0x04000000 ;;
56  mt48lc16m16a2p-6a) AC_DEFINE([ATSAM_SDRAM_MT48LC16M16A2P_6A],[1],[SDRAM variant]) EXTSDRAM=0x02000000 ;;
57  *) AC_MSG_ERROR([bad value ${enableval} for SDRAM variant]) ;;
58esac],
59[AC_DEFINE([ATSAM_SDRAM_IS42S16100E_7BLI],[1],[SDRAM variant]) EXTSDRAM=0x00200000])
60
61RTEMS_BSPOPTS_SET([BOARD_MAINOSC],[*],[12000000])
62RTEMS_BSPOPTS_HELP([BOARD_MAINOSC],[Main oscillator frequency in Hz (default 12MHz)])
63
64RTEMS_BSPOPTS_SET([ATSAM_MCK],[*],[123000000])
65RTEMS_BSPOPTS_HELP([ATSAM_MCK],
66[Frequency of the MCK in Hz. Set to 0 to force application defined speed.
67See start/pmc-config.c for available clock configurations.])
68
69RTEMS_BSPOPTS_SET([ATSAM_SLOWCLOCK_USE_XTAL],[*],[1])
70RTEMS_BSPOPTS_HELP([ATSAM_SLOWCLOCK_USE_XTAL],
71[Use the external crystal as source for the slow clock instead of the internal
72RC oscillator. Note that on the ATSAM the NRST pin seems to depend on the slow
73clock as well as all watchdogs. If ATSAM_SLOWCLOCK_USE_XTAL is set to 1 without
74a external crystal connected, the controller might hang in the switching process
75without a working NRST pin. ])
76
77RTEMS_BSPOPTS_SET([ATSAM_CHANGE_CLOCK_FROM_SRAM],[*],[0])
78RTEMS_BSPOPTS_HELP([ATSAM_CHANGE_CLOCK_FROM_SRAM],
79[Move the functions that set up the clock into the SRAM.
80This allows to change the clock frequency even if the application is started from SDRAM.
81Requires a TCM_SIZE > 0.])
82
83RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_BAUD],[*],[115200])
84RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_BAUD],[initial baud for console devices (default 115200)])
85
86RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_DEVICE_TYPE],[*],[0])
87RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_DEVICE_TYPE],[device type for /dev/console, use 0 for USART and 1 for UART (default USART)])
88
89RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_DEVICE_INDEX],[*],[1])
90RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_DEVICE_INDEX],[device index for /dev/console (default 1, e.g. USART1)])
91
92RTEMS_BSPOPTS_SET([ATSAM_CONSOLE_USE_INTERRUPTS],[*],[1])
93RTEMS_BSPOPTS_HELP([ATSAM_CONSOLE_USE_INTERRUPTS],[use interrupt driven mode for console devices (used by default)])
94
95AC_DEFUN([ATSAM_LINKCMD],[
96AC_ARG_VAR([$1],[$2])dnl
97[$1]=[$]{[$1]:-[$3]}
98])
99
100ATSAM_LINKCMD([ATSAM_MEMORY_TCM_SIZE],[size of tightly coupled memories (TCM) in bytes],[0x00000000])
101ATSAM_LINKCMD([ATSAM_MEMORY_INTFLASH_SIZE],[size of internal flash in bytes],[${INTFLASH}])
102ATSAM_LINKCMD([ATSAM_MEMORY_INTSRAM_SIZE],[size of internal SRAM in bytes],[${INTSRAM}])
103ATSAM_LINKCMD([ATSAM_MEMORY_SDRAM_SIZE],[size of external SDRAM in bytes],[${EXTSDRAM}])
104ATSAM_LINKCMD([ATSAM_MEMORY_QSPIFLASH_SIZE],[size of QSPI flash in bytes],[0x00200000])
105ATSAM_LINKCMD([ATSAM_MEMORY_NOCACHE_SIZE],[size of NOCACHE section in bytes],[0x00001000])
106
107AC_CONFIG_FILES([
108Makefile
109linkcmds.memory:../../../../../../bsps/arm/atsam/start/linkcmds.memory.in
110])
111AC_OUTPUT
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