1 | /* |
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2 | * start.S : RTEMS entry point |
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3 | * |
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4 | * Copyright (C) 2000 Canon Research Centre France SA. |
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5 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | */ |
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12 | |
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13 | .equ ABORT_Stack, 0 |
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14 | .equ IRQ_Stack, 0x100 |
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15 | .equ FIQ_Stack, 0x200 |
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16 | .equ SVC_Stack, 0x300 |
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17 | |
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18 | /* Some standard definitions...*/ |
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19 | |
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20 | .equ Mode_USR, 0x10 |
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21 | .equ Mode_FIQ, 0x11 |
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22 | .equ Mode_IRQ, 0x12 |
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23 | .equ Mode_SVC, 0x13 |
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24 | .equ Mode_ABT, 0x17 |
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25 | .equ Mode_ABORT, 0x17 |
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26 | .equ Mode_UNDEF, 0x1B |
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27 | .equ Mode_SYS, 0x1F /*only available on ARM Arch. v4*/ |
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28 | |
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29 | .equ I_Bit, 0x80 |
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30 | .equ F_Bit, 0x40 |
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31 | |
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32 | |
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33 | .text |
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34 | .globl _start |
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35 | |
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36 | |
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37 | _start: |
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38 | |
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39 | /* |
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40 | * Here is the code to initialize the low-level BSP environment |
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41 | * (Chip Select, PLL, ....?) |
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42 | |
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43 | |
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44 | /* Copy data from FLASH to RAM */ |
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45 | LDR r0, =_initdata /* load address of region */ |
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46 | LDR r1, =0x400000 /* execution address of region */ |
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47 | LDR r2, =_edata /* copy execution address into r2 */ |
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48 | |
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49 | copy: |
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50 | CMP r1, r2 /* loop whilst r1 < r2 */ |
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51 | LDRLO r3, [r0], #4 |
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52 | STRLO r3, [r1], #4 |
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53 | BLO copy |
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54 | |
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55 | /* zero the bss */ |
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56 | LDR r1, =__bss_end__ /* get end of ZI region */ |
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57 | LDR r0, =__bss_start__ /* load base address of ZI region */ |
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58 | zi_init: |
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59 | MOV r2, #0 |
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60 | CMP r0, r1 /* loop whilst r0 < r1 */ |
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61 | STRLOT r2, [r0], #4 |
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62 | BLO zi_init |
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63 | |
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64 | |
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65 | /* Load basic ARM7 interrupt table */ |
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66 | VectorInit: |
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67 | MOV R8, #0 |
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68 | ADR R9, Vector_Init_Block |
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69 | LDMIA R9!, {R0-R7} /* Copy the Vectors (8 words) */ |
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70 | STMIA R8!, {R0-R7} |
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71 | LDMIA R9!, {R0-R7} /* Copy the .long'ed addresses (8 words) */ |
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72 | STMIA R8!, {R0-R7} |
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73 | |
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74 | B init2 |
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75 | |
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76 | /******************************************************* |
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77 | standard exception vectors table |
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78 | *** Must be located at address 0 |
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79 | ********************************************************/ |
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80 | |
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81 | Vector_Init_Block: |
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82 | LDR PC, Reset_Addr |
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83 | LDR PC, Undefined_Addr |
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84 | LDR PC, SWI_Addr |
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85 | LDR PC, Prefetch_Addr |
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86 | LDR PC, Abort_Addr |
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87 | NOP |
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88 | LDR PC, IRQ_Addr |
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89 | LDR PC, FIQ_Addr |
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90 | |
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91 | .globl Reset_Addr |
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92 | Reset_Addr: .long _start |
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93 | Undefined_Addr: .long Undefined_Handler |
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94 | SWI_Addr: .long SWI_Handler |
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95 | Prefetch_Addr: .long Prefetch_Handler |
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96 | Abort_Addr: .long Abort_Handler |
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97 | .long 0 |
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98 | IRQ_Addr: .long IRQ_Handler |
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99 | FIQ_Addr: .long FIQ_Handler |
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100 | |
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101 | /* The following handlers do not do anything useful */ |
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102 | .globl Undefined_Handler |
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103 | Undefined_Handler: |
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104 | B Undefined_Handler |
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105 | .globl SWI_Handler |
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106 | SWI_Handler: |
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107 | B SWI_Handler |
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108 | .globl Prefetch_Handler |
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109 | Prefetch_Handler: |
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110 | B Prefetch_Handler |
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111 | .globl Abort_Handler |
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112 | Abort_Handler: |
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113 | B Abort_Handler |
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114 | .globl IRQ_Handler |
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115 | IRQ_Handler: |
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116 | B IRQ_Handler |
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117 | .globl FIQ_Handler |
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118 | FIQ_Handler: |
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119 | B FIQ_Handler |
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120 | |
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121 | init2 : |
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122 | /* --- Initialise stack pointer registers |
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123 | Set up the ABORT stack pointer last and stay in SVC mode */ |
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124 | MOV r0, #(Mode_ABORT | I_Bit | F_Bit) /* No interrupts */ |
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125 | MSR cpsr, r0 |
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126 | LDR sp, =ABORT_Stack |
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127 | |
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128 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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129 | MOV r0, #Mode_IRQ | I_Bit | F_Bit /* No interrupts */ |
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130 | MSR cpsr, r0 |
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131 | LDR sp, =IRQ_Stack |
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132 | |
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133 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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134 | MOV r0, #Mode_FIQ | I_Bit | F_Bit /* No interrupts */ |
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135 | MSR cpsr, r0 |
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136 | LDR sp, =FIQ_Stack |
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137 | |
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138 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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139 | MOV r0, #Mode_SVC | I_Bit | F_Bit /* No interrupts */ |
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140 | MSR cpsr, r0 |
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141 | LDR sp, =SVC_Stack |
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142 | |
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143 | /* --- Now we enter the C code */ |
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144 | |
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145 | B boot_card |
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146 | |
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147 | |
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148 | |
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149 | |
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150 | |
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157 | |
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