source: rtems/c/src/lib/libbsp/arm/arm_bare_bsp/start/start.S @ f1c62bb

4.104.114.84.95
Last change on this file since f1c62bb was 08330bf, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 27, 2000 at 1:04:11 AM

Port of RTEMS to the ARM processor family by Eric Valette
<valette@…> and Emmanuel Raguet <raguet@…>
of Canon CRF - Communication Dept. This port includes a
basic BSP that is sufficient to link hello world.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 *  start.S :     RTEMS entry point
3 *
4 *  Copyright (C) 2000 Canon Research Centre France SA.
5 *  Emmanuel Raguet, mailto:raguet@crf.canon.fr
6 *
7 *  The license and distribution terms for this file may be
8 *  found in found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 */
12
13.equ ABORT_Stack, 0
14.equ IRQ_Stack, 0x100
15.equ FIQ_Stack, 0x200
16.equ SVC_Stack, 0x300
17       
18/* Some standard definitions...*/
19
20.equ Mode_USR,               0x10
21.equ Mode_FIQ,               0x11
22.equ Mode_IRQ,               0x12
23.equ Mode_SVC,               0x13
24.equ Mode_ABT,               0x17
25.equ Mode_ABORT,             0x17
26.equ Mode_UNDEF,             0x1B
27.equ Mode_SYS,               0x1F /*only available on ARM Arch. v4*/
28
29.equ I_Bit,                  0x80
30.equ F_Bit,                  0x40
31
32
33        .text
34        .globl  _start
35
36         
37_start:
38
39/*
40 * Here is the code to initialize the low-level BSP environment
41 * (Chip Select, PLL, ....?)
42
43       
44/* Copy data from FLASH to RAM */
45        LDR     r0, =_initdata        /* load address of region */
46        LDR     r1, =0x400000         /* execution address of region */
47        LDR     r2, =_edata           /* copy execution address into r2 */
48
49copy:   
50        CMP     r1, r2                /* loop whilst r1 < r2 */
51        LDRLO   r3, [r0], #4
52        STRLO   r3, [r1], #4
53        BLO     copy
54
55/* zero the bss */
56        LDR     r1, =__bss_end__       /* get end of ZI region */
57        LDR     r0, =__bss_start__     /* load base address of ZI region */
58zi_init:       
59        MOV     r2, #0
60        CMP     r0, r1                 /* loop whilst r0 < r1 */
61        STRLOT   r2, [r0], #4
62        BLO     zi_init
63
64       
65/* Load basic ARM7 interrupt table */
66VectorInit:     
67        MOV     R8, #0
68        ADR     R9, Vector_Init_Block
69        LDMIA   R9!, {R0-R7}    /* Copy the Vectors (8 words) */
70        STMIA   R8!, {R0-R7}
71        LDMIA   R9!, {R0-R7}    /* Copy the .long'ed addresses (8 words) */
72        STMIA   R8!, {R0-R7}
73
74        B       init2
75
76/*******************************************************
77 standard exception vectors table
78 *** Must be located at address 0
79********************************************************/       
80
81Vector_Init_Block:     
82        LDR     PC, Reset_Addr
83        LDR     PC, Undefined_Addr
84        LDR     PC, SWI_Addr
85        LDR     PC, Prefetch_Addr
86        LDR     PC, Abort_Addr
87        NOP
88        LDR     PC, IRQ_Addr
89        LDR     PC, FIQ_Addr
90
91        .globl Reset_Addr
92Reset_Addr:     .long   _start
93Undefined_Addr: .long   Undefined_Handler
94SWI_Addr:       .long   SWI_Handler
95Prefetch_Addr:  .long   Prefetch_Handler
96Abort_Addr:     .long   Abort_Handler
97                .long   0       
98IRQ_Addr:       .long   IRQ_Handler
99FIQ_Addr:       .long   FIQ_Handler
100       
101/* The following handlers do not do anything useful */
102        .globl Undefined_Handler
103Undefined_Handler:     
104        B       Undefined_Handler
105        .globl SWI_Handler
106SWI_Handler:   
107        B       SWI_Handler
108        .globl Prefetch_Handler
109Prefetch_Handler:       
110        B       Prefetch_Handler
111        .globl Abort_Handler
112Abort_Handler: 
113        B       Abort_Handler
114        .globl IRQ_Handler
115IRQ_Handler:   
116        B       IRQ_Handler
117        .globl FIQ_Handler
118FIQ_Handler:   
119        B       FIQ_Handler
120
121init2 :
122/* --- Initialise stack pointer registers
123   Set up the ABORT stack pointer last and stay in SVC mode */
124    MOV     r0, #(Mode_ABORT | I_Bit | F_Bit)   /* No interrupts */
125    MSR     cpsr, r0
126    LDR     sp, =ABORT_Stack
127
128/* Enter IRQ mode and set up the IRQ stack pointer */
129    MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
130    MSR     cpsr, r0
131    LDR     sp, =IRQ_Stack
132
133/* Enter FIQ mode and set up the FIQ stack pointer */
134    MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
135    MSR     cpsr, r0
136    LDR     sp, =FIQ_Stack
137
138/* Set up the SVC stack pointer last and stay in SVC mode */
139    MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
140    MSR     cpsr, r0
141    LDR     sp, =SVC_Stack
142
143/* --- Now we enter the C code */
144
145    B   boot_card
146
147
148
149
150
151
152
153
154
155
156
157
Note: See TracBrowser for help on using the repository browser.