source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit @ f73cfe99

4.115
Last change on this file since f73cfe99 was f73cfe99, checked in by Ralf Kirchner <ralf.kirchner@…>, on Jul 31, 2013 at 7:45:59 AM

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
  • Property mode set to 100644
File size: 575 bytes
Line 
1MEMORY {
2   RAM_MMU : ORIGIN = 0x00100000, LENGTH = 16k
3   NOCACHE : ORIGIN = 0x00200000, LENGTH = 1M
4   RAM     : ORIGIN = 0x00300000, LENGTH = 1024M - 1M - 1M - 1M
5}
6
7SECTIONS {
8  .nocache : {
9    bsp_section_nocache_begin = .;
10    *(SORT(.bsp_nocache*))
11    bsp_section_nocache_end = .;
12  } > NOCACHE AT > NOCACHE
13  bsp_section_nocache_size = bsp_section_nocache_end - bsp_section_nocache_begin;
14  bsp_section_nocache_load_begin = LOADADDR (.nocache);
15  bsp_section_nocache_load_end = bsp_section_nocache_load_begin + bsp_section_nocache_size;
16}
17
18INCLUDE linkcmds.altcycv
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