4.115
Last change
on this file since 0b03ca39 was
f73cfe99,
checked in by Ralf Kirchner <ralf.kirchner@…>, on 07/31/13 at 07:45:59
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bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
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-
Property mode set to
100644
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File size:
575 bytes
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1 | MEMORY { |
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2 | RAM_MMU : ORIGIN = 0x00100000, LENGTH = 16k |
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3 | NOCACHE : ORIGIN = 0x00200000, LENGTH = 1M |
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4 | RAM : ORIGIN = 0x00300000, LENGTH = 1024M - 1M - 1M - 1M |
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5 | } |
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6 | |
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7 | SECTIONS { |
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8 | .nocache : { |
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9 | bsp_section_nocache_begin = .; |
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10 | *(SORT(.bsp_nocache*)) |
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11 | bsp_section_nocache_end = .; |
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12 | } > NOCACHE AT > NOCACHE |
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13 | bsp_section_nocache_size = bsp_section_nocache_end - bsp_section_nocache_begin; |
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14 | bsp_section_nocache_load_begin = LOADADDR (.nocache); |
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15 | bsp_section_nocache_load_end = bsp_section_nocache_load_begin + bsp_section_nocache_size; |
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16 | } |
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17 | |
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18 | INCLUDE linkcmds.altcycv |
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