source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c @ f73cfe99

4.115
Last change on this file since f73cfe99 was f73cfe99, checked in by Ralf Kirchner <ralf.kirchner@…>, on Jul 31, 2013 at 7:45:59 AM

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
  • Property mode set to 100644
File size: 6.1 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#include <bsp.h>
16#include <bsp/start.h>
17#include <bsp/arm-cp15-start.h>
18#include <bsp/arm-a9mpcore-start.h>
19#include <bsp/linker-symbols.h>
20#include <alt_address_space.h>
21#include "socal/socal.h"
22#include "socal/alt_sdr.h"
23#include "socal/hps.h"
24#include "../include/arm-cache-l1.h"
25
26/*#define DEBUG_ECC_ERROR*/ /* TODO: Delete DEBUG_ECC_ERROR after the implementation phase */
27
28#ifdef RTEMS_SMP
29  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE
30#else
31  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED
32#endif
33
34/* 1 MB reset default value for address filtering start */
35#define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
36
37#ifndef BSPSTARTHOOKS_MIN
38#define BSPSTARTHOOKS_MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) )
39#endif
40
41LINKER_SYMBOL( bsp_section_nocache_size );
42LINKER_SYMBOL( bsp_section_nocache_end );
43LINKER_SYMBOL( bsp_section_nocache_begin );
44
45BSP_START_DATA_SECTION static const arm_cp15_start_section_config
46  altcycv_mmu_config_table[] = {
47  ARMV7_CP15_START_DEFAULT_SECTIONS,
48  {
49    .begin = (uint32_t) bsp_section_nocache_begin,
50    .end   = (uint32_t) bsp_section_nocache_end,
51
52    .flags = ARMV7_MMU_DATA_READ_WRITE | ARM_MMU_SECT_TEX_0
53  }, { /* Periphery area */
54    .begin = 0xFC000000U,
55    .end   = 0x00000000U,
56    .flags = ARMV7_MMU_DEVICE
57  }
58};
59
60BSP_START_TEXT_SECTION static void setup_mmu_and_cache( const uint32_t CPU_ID )
61{
62  uint32_t       ctrl  = arm_cp15_get_control();
63  const uint32_t CORES = BSPSTARTHOOKS_MIN(
64    (uintptr_t) bsp_processor_count,
65    rtems_configuration_get_maximum_processors() );
66
67  /* We expect the L1 caches and program flow prediction to be off */
68  assert( ( ctrl & ARM_CP15_CTRL_I ) == 0 );
69  assert( ( ctrl & ARM_CP15_CTRL_C ) == 0 );
70  assert( ( ctrl & ARM_CP15_CTRL_Z ) == 0 );
71
72  ctrl = arm_cp15_start_setup_mmu_and_cache(
73    ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
74    ARM_CP15_CTRL_AFE
75    );
76
77  if( CPU_ID == 0 ) {
78    arm_cp15_start_setup_translation_table(
79      (uint32_t *) bsp_translation_table_base,
80      ARM_MMU_DEFAULT_CLIENT_DOMAIN,
81      &altcycv_mmu_config_table[0],
82      RTEMS_ARRAY_SIZE( altcycv_mmu_config_table )
83    );
84  } else {
85    /* FIXME: Sharing the translation table between processors is brittle */
86    arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base);
87  }
88
89  /* Enable MMU */
90  ctrl |= ARM_CP15_CTRL_M;
91
92  arm_cp15_set_control( ctrl );
93 
94  if( CPU_ID == (CORES - 1) ) {
95    /* Enable all cache levels for the last core */
96    rtems_cache_enable_instruction();
97    rtems_cache_enable_data();
98  } else {
99    /* Enable only L1 cache */
100    arm_cache_l1_enable_data();
101    arm_cache_l1_enable_instruction();
102  }
103
104  /* Enable flow control prediction aka. branch prediction */
105
106/* TODO: With the current network stack 06-Feb2014 in_checksum()
107 * becomes a severe performance bottle neck with branch prediction enabled
108   ctrl |= ARM_CP15_CTRL_Z;
109   arm_cp15_set_control(ctrl);*/
110}
111
112BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
113{
114  uint32_t ctrl;
115  volatile a9mpcore_scu *scu    = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
116  uint32_t               cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
117  const uint32_t         CORES  = BSPSTARTHOOKS_MIN(
118    (uintptr_t) bsp_processor_count,
119    rtems_configuration_get_maximum_processors() );
120 
121  assert( cpu_id < CORES );
122 
123  if( cpu_id < CORES ) {
124    if( cpu_id == 0 ) {
125      ctrl = arm_cp15_mmu_disable( 32 );
126
127      ctrl &= ~( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_Z );
128      arm_cp15_set_control( ctrl );
129     
130      /* Enable Snoop Control Unit (SCU) */
131      arm_a9mpcore_start_scu_enable( scu );
132    }
133
134#ifdef RTEMS_SMP
135    /* Enable cache coherency support for this processor */
136    uint32_t actlr = arm_cp15_get_auxiliary_control();
137    actlr |= ARM_CORTEX_A9_ACTL_SMP;
138    arm_cp15_set_auxiliary_control(actlr);
139#endif
140
141    if (cpu_id == 0) {
142      arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF);
143    }
144   
145    setup_mmu_and_cache( cpu_id );
146   
147#ifdef RTEMS_SMP
148    if (cpu_id != 0) {
149      arm_a9mpcore_start_set_vector_base();
150
151      arm_gic_irq_initialize_secondary_cpu();
152
153      arm_cp15_set_domain_access_control(
154        ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
155      );
156      _SMP_Start_multitasking_on_secondary_processor();
157    }
158#endif
159  } else {
160    /* FIXME: Shutdown processor */
161    while (1) {
162      __asm__ volatile ("wfi");
163    }
164  }
165}
166
167BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
168{
169  uint32_t addr_filt_start;
170  uint32_t addr_filt_end;
171
172  /* Disable ECC. Preloader respectively UBoot enable ECC.
173     But they do run without interrupts. Our BSP will enable interrupts
174     and get spurious ECC error interrupts. Thus we disasable ECC
175     until we either know about a better handling or Altera has modified
176     it's SDRAM settings to not create possibly false ECC errors */
177  uint32_t ctlcfg = alt_read_word( ALT_SDR_CTL_CTLCFG_ADDR );
178  ctlcfg &= ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK;
179  alt_write_word( ALT_SDR_CTL_CTLCFG_ADDR, ctlcfg );
180
181  /* Perform L3 remap register programming first by setting the desired new MPU
182     address space 0 mapping. Assume BOOTROM in order to be able to boot the
183     second core. */
184  alt_addr_space_remap(
185    ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
186    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,
187    ALT_ADDR_SPACE_H2F_ACCESSIBLE,
188    ALT_ADDR_SPACE_LWH2F_ACCESSIBLE );
189
190  /* Next, adjust the L2 cache address filtering range. Set the start address
191   * to the default reset value and retain the existing end address
192   * configuration. */
193  alt_l2_addr_filter_cfg_get( &addr_filt_start, &addr_filt_end );
194
195  if ( addr_filt_start != BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET ) {
196    alt_l2_addr_filter_cfg_set( BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET,
197                                addr_filt_end );
198  }
199
200  arm_a9mpcore_start_hook_1();
201  bsp_start_copy_sections();
202
203  bsp_start_clear_bss();
204}
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