1 | /* |
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2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <bsp/start.h> |
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19 | #include <bsp/arm-cp15-start.h> |
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20 | #include <bsp/arm-a9mpcore-start.h> |
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21 | #include <bsp/linker-symbols.h> |
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22 | #include <bsp/alt_address_space.h> |
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23 | #include <bsp/socal/socal.h> |
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24 | #include <bsp/socal/alt_sdr.h> |
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25 | #include <bsp/socal/hps.h> |
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26 | |
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27 | /* 1 MB reset default value for address filtering start */ |
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28 | #define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000 |
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29 | |
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30 | BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) |
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31 | { |
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32 | arm_cp15_instruction_cache_invalidate(); |
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33 | arm_cp15_data_cache_invalidate_all_levels(); |
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34 | arm_a9mpcore_start_hook_0(); |
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35 | } |
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36 | |
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37 | BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void) |
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38 | { |
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39 | uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache( |
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40 | ARM_CP15_CTRL_A | ARM_CP15_CTRL_M, |
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41 | ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z |
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42 | ); |
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43 | |
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44 | arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( |
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45 | ctrl, |
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46 | (uint32_t *) bsp_translation_table_base, |
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47 | ARM_MMU_DEFAULT_CLIENT_DOMAIN, |
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48 | &arm_cp15_start_mmu_config_table[0], |
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49 | arm_cp15_start_mmu_config_table_size |
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50 | ); |
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51 | } |
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52 | |
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53 | BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) |
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54 | { |
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55 | uint32_t addr_filt_start; |
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56 | uint32_t addr_filt_end; |
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57 | |
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58 | /* Disable ECC. Preloader respectively UBoot enable ECC. |
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59 | But they do run without interrupts. Our BSP will enable interrupts |
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60 | and get spurious ECC error interrupts. Thus we disasable ECC |
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61 | until we either know about a better handling or Altera has modified |
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62 | it's SDRAM settings to not create possibly false ECC errors */ |
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63 | uint32_t ctlcfg = alt_read_word( ALT_SDR_CTL_CTLCFG_ADDR ); |
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64 | ctlcfg &= ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK; |
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65 | alt_write_word( ALT_SDR_CTL_CTLCFG_ADDR, ctlcfg ); |
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66 | |
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67 | /* Perform L3 remap register programming first by setting the desired new MPU |
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68 | address space 0 mapping. Assume BOOTROM in order to be able to boot the |
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69 | second core. */ |
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70 | alt_addr_space_remap( |
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71 | ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, |
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72 | ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, |
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73 | ALT_ADDR_SPACE_H2F_ACCESSIBLE, |
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74 | ALT_ADDR_SPACE_LWH2F_ACCESSIBLE ); |
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75 | |
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76 | /* Next, adjust the L2 cache address filtering range. Set the start address |
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77 | * to the default reset value and retain the existing end address |
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78 | * configuration. */ |
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79 | alt_l2_addr_filter_cfg_get( &addr_filt_start, &addr_filt_end ); |
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80 | |
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81 | if ( addr_filt_start != BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET ) { |
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82 | alt_l2_addr_filter_cfg_set( BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET, |
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83 | addr_filt_end ); |
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84 | } |
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85 | |
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86 | arm_a9mpcore_start_hook_1(); |
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87 | bsp_start_copy_sections(); |
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88 | setup_mmu_and_cache(); |
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89 | #ifndef RTEMS_SMP |
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90 | /* Enable unified L2 cache */ |
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91 | rtems_cache_enable_data(); |
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92 | #endif |
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93 | bsp_start_clear_bss(); |
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94 | } |
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