1 | /* |
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2 | * Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/bootcard.h> |
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16 | #include <bsp/arm-a9mpcore-clock.h> |
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17 | #include <bsp/fdt.h> |
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18 | #include <bsp/irq-generic.h> |
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19 | #include <bsp/linker-symbols.h> |
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20 | |
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21 | #include <alt_clock_manager.h> |
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22 | |
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23 | #include <libfdt.h> |
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24 | |
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25 | static void set_clock( |
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26 | const void *fdt, |
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27 | int parent, |
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28 | ALT_CLK_t clk, |
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29 | const char *name |
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30 | ) |
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31 | { |
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32 | int node; |
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33 | int len; |
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34 | const uint32_t *val; |
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35 | |
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36 | node = fdt_subnode_offset(fdt, parent, name); |
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37 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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38 | |
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39 | if (val != NULL && len >= 4) { |
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40 | alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0])); |
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41 | } |
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42 | } |
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43 | |
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44 | static void set_clock_by_output_name( |
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45 | const void *fdt, |
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46 | ALT_CLK_t clk, |
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47 | const char *clock_output_name |
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48 | ) |
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49 | { |
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50 | int node; |
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51 | int len; |
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52 | const uint32_t *val; |
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53 | |
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54 | node = fdt_node_offset_by_prop_value( |
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55 | fdt, |
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56 | -1, |
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57 | "clock-output-names", |
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58 | clock_output_name, |
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59 | strlen(clock_output_name) + 1 |
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60 | ); |
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61 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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62 | |
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63 | if (val != NULL && len >= 4) { |
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64 | alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0])); |
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65 | } |
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66 | } |
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67 | |
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68 | static void update_clocks(void) |
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69 | { |
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70 | const void *fdt; |
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71 | int parent; |
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72 | |
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73 | fdt = bsp_fdt_get(); |
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74 | |
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75 | /* Try to set by node name */ |
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76 | parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr"); |
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77 | parent = fdt_subnode_offset(fdt, parent, "clocks"); |
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78 | set_clock(fdt, parent, ALT_CLK_OSC1, "osc1"); |
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79 | set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2"); |
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80 | set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk"); |
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81 | set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk"); |
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82 | |
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83 | /* Try to set by "clock-output-names" property value */ |
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84 | set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk"); |
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85 | set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk"); |
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86 | set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk"); |
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87 | set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk"); |
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88 | } |
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89 | |
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90 | void bsp_start(void) |
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91 | { |
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92 | update_clocks(); |
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93 | a9mpcore_clock_initialize_early(); |
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94 | bsp_interrupt_initialize(); |
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95 | rtems_cache_coherent_add_area( |
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96 | bsp_section_nocacheheap_begin, |
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97 | (uintptr_t) bsp_section_nocacheheap_size |
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98 | ); |
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99 | } |
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