source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstart.c @ 3454179

Last change on this file since 3454179 was 3454179, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 5, 2018 at 12:54:48 PM

bsp/altera-cyclone-v: Add device tree support

Update #3290.

  • Property mode set to 100644
File size: 2.5 KB
Line 
1/*
2 * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp/bootcard.h>
16#include <bsp/arm-a9mpcore-clock.h>
17#include <bsp/fdt.h>
18#include <bsp/irq-generic.h>
19#include <bsp/linker-symbols.h>
20
21#include <bsp/alt_clock_manager.h>
22
23#include <libfdt.h>
24
25uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
26{
27  return intr[1] + 32;
28}
29
30static void set_clock(
31  const void *fdt,
32  int parent,
33  ALT_CLK_t clk,
34  const char *name
35)
36{
37  int node;
38  int len;
39  const uint32_t *val;
40
41  node = fdt_subnode_offset(fdt, parent, name);
42  val = fdt_getprop(fdt, node, "clock-frequency", &len);
43
44  if (val != NULL && len >= 4) {
45    alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
46  }
47}
48
49static void set_clock_by_output_name(
50  const void *fdt,
51  ALT_CLK_t clk,
52  const char *clock_output_name
53)
54{
55  int node;
56  int len;
57  const uint32_t *val;
58
59  node = fdt_node_offset_by_prop_value(
60    fdt,
61    -1,
62    "clock-output-names",
63    clock_output_name,
64    strlen(clock_output_name) + 1
65  );
66  val = fdt_getprop(fdt, node, "clock-frequency", &len);
67
68  if (val != NULL && len >= 4) {
69    alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
70  }
71}
72
73static void update_clocks(void)
74{
75  const void *fdt;
76  int parent;
77
78  fdt = bsp_fdt_get();
79
80  /* Try to set by node name */
81  parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr");
82  parent = fdt_subnode_offset(fdt, parent, "clocks");
83  set_clock(fdt, parent, ALT_CLK_OSC1, "osc1");
84  set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2");
85  set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk");
86  set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk");
87
88  /* Try to set by "clock-output-names" property value */
89  set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk");
90  set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk");
91  set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk");
92  set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk");
93}
94
95void bsp_start(void)
96{
97  update_clocks();
98  a9mpcore_clock_initialize_early();
99  bsp_interrupt_initialize();
100  rtems_cache_coherent_add_area(
101    bsp_section_nocacheheap_begin,
102    (uintptr_t) bsp_section_nocacheheap_size
103  );
104}
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