source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c @ 50440c0

4.115
Last change on this file since 50440c0 was 50440c0, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 19, 2014 at 2:30:24 PM

bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs

  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*
2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <rtems/score/smpimpl.h>
16
17#include <bsp/start.h>
18
19#include <socal/alt_rstmgr.h>
20#include <socal/alt_sysmgr.h>
21#include <socal/hps.h>
22#include <socal/socal.h>
23
24bool _CPU_SMP_Start_processor(uint32_t cpu_index)
25{
26  bool started;
27
28  if (cpu_index == 1) {
29    alt_write_word(
30      ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST,
31      ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start)
32    );
33
34    alt_clrbits_word(
35      ALT_RSTMGR_MPUMODRST_ADDR,
36      ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
37    );
38
39    /*
40     * Wait for secondary processor to complete its basic initialization so
41     * that we can enable the unified L2 cache.
42     */
43    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
44  } else {
45    started = false;
46  }
47
48  return started;
49}
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