source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/make/custom/altcycv.inc @ f73cfe99

4.115
Last change on this file since f73cfe99 was f73cfe99, checked in by Ralf Kirchner <ralf.kirchner@…>, on Jul 31, 2013 at 7:45:59 AM

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
  • Property mode set to 100644
File size: 203 bytes
Line 
1include $(RTEMS_ROOT)/make/custom/default.cfg
2
3RTEMS_CPU = arm
4
5CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
6
7#CFLAGS_OPTIMIZE_V ?= -O0 -g
8CFLAGS_OPTIMIZE_V ?= -O2 -g
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