4.115
Last change
on this file since 0b03ca39 was
f73cfe99,
checked in by Ralf Kirchner <ralf.kirchner@…>, on 07/31/13 at 07:45:59
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bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
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-
Property mode set to
100644
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File size:
203 bytes
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1 | include $(RTEMS_ROOT)/make/custom/default.cfg |
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2 | |
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3 | RTEMS_CPU = arm |
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4 | |
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5 | CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 |
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6 | |
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7 | #CFLAGS_OPTIMIZE_V ?= -O0 -g |
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8 | CFLAGS_OPTIMIZE_V ?= -O2 -g |
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