1 | /****************************************************************************** |
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2 | * |
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3 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions are met: |
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7 | * |
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8 | * 1. Redistributions of source code must retain the above copyright notice, |
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9 | * this list of conditions and the following disclaimer. |
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10 | * |
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11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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12 | * this list of conditions and the following disclaimer in the documentation |
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13 | * and/or other materials provided with the distribution. |
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14 | * |
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15 | * 3. The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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27 | * OF SUCH DAMAGE. |
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28 | * |
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29 | ******************************************************************************/ |
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30 | |
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31 | /*! \file |
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32 | * Altera - QSPI Flash Controller Module |
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33 | */ |
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34 | |
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35 | #ifndef __ALT_QSPI_PRIVATE_H__ |
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36 | #define __ALT_QSPI_PRIVATE_H__ |
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37 | |
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38 | #include "socal/socal.h" |
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39 | |
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40 | // |
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41 | // This section provisions support for various flash devices. |
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42 | // |
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43 | |
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44 | #define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1 |
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45 | |
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46 | ///// |
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47 | |
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48 | #define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00 |
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49 | #define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B |
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50 | #define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000 |
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51 | #define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B |
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52 | #define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000 |
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53 | #define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB |
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54 | #define ALT_QSPI_BANK_ADDR_MSK 0xFF000000 |
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55 | #define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB |
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56 | |
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57 | #if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT |
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58 | #define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000 |
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59 | #define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB |
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60 | #endif |
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61 | |
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62 | ///// |
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63 | |
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64 | // Default delay timing (in ns) for N25Q. |
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65 | // These values are from the N25Q handbook. The timing correctness is difficult |
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66 | // to test because the test setup does not feature mutliple chips. |
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67 | #define ALT_QSPI_TSHSL_NS_DEF (50) |
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68 | #define ALT_QSPI_TSD2D_NS_DEF (0) |
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69 | #define ALT_QSPI_TCHSH_NS_DEF (4) |
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70 | #define ALT_QSPI_TSLCH_NS_DEF (4) |
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71 | |
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72 | /* |
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73 | // Default delay timing (in ns) |
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74 | #define ALT_QSPI_TSHSL_NS_DEF (200) |
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75 | #define ALT_QSPI_TSD2D_NS_DEF (255) |
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76 | #define ALT_QSPI_TCHSH_NS_DEF (20) |
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77 | #define ALT_QSPI_TSLCH_NS_DEF (20) |
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78 | */ |
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79 | |
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80 | // Flash commands |
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81 | #define ALT_QSPI_STIG_OPCODE_READ (0x03) |
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82 | #define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13) |
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83 | #define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B) |
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84 | #define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B) |
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85 | #define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B) |
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86 | #define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB) |
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87 | #define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB) |
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88 | #define ALT_QSPI_STIG_OPCODE_PP (0x02) |
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89 | #define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2) |
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90 | #define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32) |
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91 | #define ALT_QSPI_STIG_OPCODE_RDID (0x9F) |
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92 | #define ALT_QSPI_STIG_OPCODE_WREN (0x06) |
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93 | #define ALT_QSPI_STIG_OPCODE_WRDIS (0x04) |
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94 | #define ALT_QSPI_STIG_OPCODE_RDSR (0x05) |
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95 | #define ALT_QSPI_STIG_OPCODE_WRSR (0x01) |
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96 | #define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20) |
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97 | #define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8) |
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98 | #define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7) |
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99 | #define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4) |
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100 | #define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60) |
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101 | #define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8) |
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102 | #define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5) |
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103 | #define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05) |
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104 | #define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01) |
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105 | #define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7) |
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106 | #define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9) |
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107 | |
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108 | // Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts. |
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109 | #if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT |
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110 | #define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66) |
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111 | #define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99) |
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112 | #define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70) |
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113 | #define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50) |
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114 | #define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A) |
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115 | #endif |
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116 | |
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117 | // Spansion commands |
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118 | // #define OPCODE_ECRM (0xFF) // Exit continuous read mode |
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119 | |
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120 | #define QSPI_READ_CLK_MHZ (50) |
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121 | #define QSPI_FASTREAD_CLK_MHZ (100) |
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122 | |
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123 | // Manufacturer ID |
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124 | #define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20) |
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125 | #define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron |
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126 | #define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF) |
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127 | #define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion |
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128 | #define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2) |
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129 | #define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F) |
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130 | |
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131 | #define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff) |
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132 | #define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff) |
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133 | |
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134 | #define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1) |
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135 | #define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1) |
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136 | #define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1) |
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137 | #define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1) |
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138 | #define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1) |
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139 | #define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1) |
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140 | #define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1) |
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141 | |
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142 | #define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1) |
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143 | |
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144 | ///// |
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145 | |
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146 | #define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff) |
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147 | |
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148 | ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size); |
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149 | |
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150 | ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout); |
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151 | ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy, |
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152 | uint32_t num_bytes, uint32_t * output, |
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153 | uint32_t timeout); |
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154 | ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy, |
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155 | uint32_t num_bytes, const uint32_t * input, |
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156 | uint32_t timeout); |
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157 | ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy, |
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158 | uint32_t address, |
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159 | uint32_t timeout); |
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160 | |
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161 | ALT_STATUS_CODE alt_qspi_device_wren(void); |
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162 | ALT_STATUS_CODE alt_qspi_device_wrdis(void); |
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163 | ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid); |
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164 | ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param); |
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165 | ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank); |
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166 | |
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167 | #endif // __ALT_PRIVATE_QSPI_H__ |
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