source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_qspi_private.h @ 76386c1

4.115
Last change on this file since 76386c1 was 76386c1, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 26, 2014 at 2:00:44 PM

bsp/altera-cyclone-v: Add DMA support hwlib files

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1/******************************************************************************
2 *
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27 * OF SUCH DAMAGE.
28 *
29 ******************************************************************************/
30
31/*! \file
32 *  Altera - QSPI Flash Controller Module
33 */
34
35#ifndef __ALT_QSPI_PRIVATE_H__
36#define __ALT_QSPI_PRIVATE_H__
37
38#include "socal/socal.h"
39
40//
41// This section provisions support for various flash devices.
42//
43
44#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
45
46/////
47
48#define ALT_QSPI_PAGE_ADDR_MSK          0xFFFFFF00
49#define ALT_QSPI_PAGE_SIZE              0x00000100 // 256 B
50#define ALT_QSPI_SUBSECTOR_ADDR_MSK     0xFFFFF000
51#define ALT_QSPI_SUBSECTOR_SIZE         0x00001000 // 4096 B
52#define ALT_QSPI_SECTOR_ADDR_MSK        0xFFFF0000
53#define ALT_QSPI_SECTOR_SIZE            0x00010000 // 64 KiB
54#define ALT_QSPI_BANK_ADDR_MSK          0xFF000000
55#define ALT_QSPI_BANK_SIZE              0x01000000 // 16 MiB
56
57#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
58#define ALT_QSPI_N25Q_DIE_ADDR_MSK      0xFE000000
59#define ALT_QSPI_N25Q_DIE_SIZE          0x02000000 // 32 MiB
60#endif
61
62/////
63
64// Default delay timing (in ns) for N25Q.
65// These values are from the N25Q handbook. The timing correctness is difficult
66// to test because the test setup does not feature mutliple chips.
67#define ALT_QSPI_TSHSL_NS_DEF       (50)
68#define ALT_QSPI_TSD2D_NS_DEF       (0)
69#define ALT_QSPI_TCHSH_NS_DEF       (4)
70#define ALT_QSPI_TSLCH_NS_DEF       (4)
71
72/*
73// Default delay timing (in ns)
74#define ALT_QSPI_TSHSL_NS_DEF       (200)
75#define ALT_QSPI_TSD2D_NS_DEF       (255)
76#define ALT_QSPI_TCHSH_NS_DEF       (20)
77#define ALT_QSPI_TSLCH_NS_DEF       (20)
78*/
79
80// Flash commands
81#define ALT_QSPI_STIG_OPCODE_READ                 (0x03)
82#define ALT_QSPI_STIG_OPCODE_4BYTE_READ           (0x13)
83#define ALT_QSPI_STIG_OPCODE_FASTREAD             (0x0B)
84#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
85#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
86#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO     (0xBB)
87#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO     (0xEB)
88#define ALT_QSPI_STIG_OPCODE_PP                   (0x02)
89#define ALT_QSPI_STIG_OPCODE_DUAL_PP              (0xA2)
90#define ALT_QSPI_STIG_OPCODE_QUAD_PP              (0x32)
91#define ALT_QSPI_STIG_OPCODE_RDID                 (0x9F)
92#define ALT_QSPI_STIG_OPCODE_WREN                 (0x06)
93#define ALT_QSPI_STIG_OPCODE_WRDIS                (0x04)
94#define ALT_QSPI_STIG_OPCODE_RDSR                 (0x05)
95#define ALT_QSPI_STIG_OPCODE_WRSR                 (0x01)
96#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE         (0x20)
97#define ALT_QSPI_STIG_OPCODE_SEC_ERASE            (0xD8)
98#define ALT_QSPI_STIG_OPCODE_BULK_ERASE           (0xC7)
99#define ALT_QSPI_STIG_OPCODE_DIE_ERASE            (0xC4)
100#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE           (0x60)
101#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG           (0xC8)
102#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG           (0xC5)
103#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG          (0x05)
104#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG          (0x01)
105#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE     (0xB7)
106#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE      (0xE9)
107
108// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
109#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
110#define ALT_QSPI_STIG_OPCODE_RESET_EN             (0x66)
111#define ALT_QSPI_STIG_OPCODE_RESET_MEM            (0x99)
112#define ALT_QSPI_STIG_OPCODE_RDFLGSR              (0x70)
113#define ALT_QSPI_STIG_OPCODE_CLRFLGSR             (0x50)
114#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM         (0x5A)
115#endif
116
117// Spansion commands
118// #define OPCODE_ECRM                 (0xFF) // Exit continuous read mode
119
120#define QSPI_READ_CLK_MHZ           (50)
121#define QSPI_FASTREAD_CLK_MHZ       (100)
122
123// Manufacturer ID
124#define ALT_QSPI_STIG_RDID_JEDECID_MICRON      (0x20)
125#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX     (0x20) // Same as Micron
126#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION    (0xEF)
127#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND     (0xEF) // Same as Spansion
128#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC    (0xC2)
129#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL       (0x1F)
130
131#define ALT_QSPI_STIG_RDID_JEDECID_GET(value)    ((value >>  0) & 0xff)
132#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
133
134#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
135#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value)        ((value >> 7) & 0x1)
136#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value)      ((value >> 7) & 0x1)
137#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value)        ((value >> 5) & 0x1)
138#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value)      ((value >> 4) & 0x1)
139#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value)    ((value >> 1) & 0x1)
140#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value)   ((value >> 0) & 0x1)
141
142#define ALT_QSPI_STIG_SR_BUSY_GET(value)                          ((value >> 0) & 0x1)
143
144/////
145
146#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
147
148ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
149
150ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
151ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
152                                     uint32_t num_bytes, uint32_t * output,
153                                     uint32_t timeout);
154ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
155                                     uint32_t num_bytes, const uint32_t * input,
156                                     uint32_t timeout);
157ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
158                                       uint32_t address,
159                                       uint32_t timeout);
160
161ALT_STATUS_CODE alt_qspi_device_wren(void);
162ALT_STATUS_CODE alt_qspi_device_wrdis(void);
163ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
164ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
165ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
166
167#endif // __ALT_PRIVATE_QSPI_H__
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