1 | /****************************************************************************** |
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2 | * |
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3 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions are met: |
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7 | * |
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8 | * 1. Redistributions of source code must retain the above copyright notice, |
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9 | * this list of conditions and the following disclaimer. |
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10 | * |
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11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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12 | * this list of conditions and the following disclaimer in the documentation |
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13 | * and/or other materials provided with the distribution. |
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14 | * |
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15 | * 3. The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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27 | * OF SUCH DAMAGE. |
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28 | * |
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29 | ******************************************************************************/ |
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30 | |
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31 | #ifndef __ALT_INT_COMMON_H__ |
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32 | #define __ALT_INT_COMMON_H__ |
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33 | |
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34 | #include "hwlib.h" |
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35 | #include <stdbool.h> |
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36 | #include <stddef.h> |
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37 | |
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38 | #ifdef __cplusplus |
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39 | extern "C" |
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40 | { |
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41 | #endif |
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42 | |
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43 | /*! |
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44 | * \addtogroup INT_COMMON Interrupt Controller Common Definitions |
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45 | * |
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46 | * This module contains the definitions common to the Interrupt Controller |
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47 | * Low-Level API and Interrupt Controller Manager Interface. |
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48 | * |
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49 | * @{ |
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50 | */ |
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51 | |
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52 | /*! |
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53 | * This type definition enumerates all the interrupt identification types. |
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54 | */ |
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55 | typedef enum ALT_INT_INTERRUPT_e |
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56 | { |
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57 | ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */ |
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58 | ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */ |
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59 | ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */ |
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60 | ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */ |
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61 | ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */ |
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62 | ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */ |
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63 | ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */ |
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64 | ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */ |
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65 | ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */ |
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66 | ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */ |
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67 | ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */ |
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68 | ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */ |
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69 | ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */ |
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70 | ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */ |
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71 | ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */ |
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72 | ALT_INT_INTERRUPT_SGI15 = 15, |
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73 | /*!< |
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74 | * Software Generated Interrupts (SGI), 0 - 15. |
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75 | * * All interrupts in this group are software triggered. |
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76 | */ |
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77 | |
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78 | ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */ |
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79 | ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */ |
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80 | ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */ |
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81 | /*!< |
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82 | * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU |
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83 | * private timer, and watchdog timer. |
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84 | * * All interrupts in this group are edge triggered. |
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85 | */ |
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86 | |
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87 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */ |
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88 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */ |
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89 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */ |
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90 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */ |
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91 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */ |
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92 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */ |
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93 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */ |
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94 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */ |
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95 | ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */ |
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96 | ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */ |
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97 | ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */ |
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98 | ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */ |
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99 | ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */ |
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100 | ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */ |
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101 | ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */ |
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102 | ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47, |
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103 | /*!< |
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104 | * Interrupts sourced from CPU0. |
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105 | * |
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106 | * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the |
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107 | * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts |
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108 | * for CPU0. |
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109 | * |
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110 | * * PARITYFAIL interrupts in this group are edge triggered. |
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111 | * * DEFFLAGS interrupts in this group are level triggered. |
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112 | */ |
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113 | |
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114 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */ |
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115 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */ |
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116 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */ |
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117 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */ |
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118 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */ |
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119 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */ |
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120 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */ |
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121 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */ |
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122 | ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */ |
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123 | ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */ |
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124 | ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */ |
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125 | ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */ |
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126 | ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */ |
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127 | ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */ |
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128 | ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */ |
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129 | ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63, |
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130 | /*!< |
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131 | * Interrupts sourced from CPU1. |
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132 | * |
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133 | * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the |
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134 | * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts |
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135 | * for CPU1. |
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136 | * |
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137 | * * PARITYFAIL interrupts in this group are edge triggered. |
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138 | * * DEFFLAGS interrupts in this group are level triggered. |
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139 | */ |
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140 | |
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141 | ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */ |
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142 | ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */ |
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143 | ALT_INT_INTERRUPT_SCU_EV_ABORT = 66, |
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144 | /*!< |
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145 | * Interrupts sourced from the Snoop Control Unit (SCU). |
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146 | * * All interrupts in this group are edge triggered. |
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147 | */ |
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148 | |
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149 | ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */ |
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150 | ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */ |
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151 | ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */ |
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152 | ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70, |
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153 | /*!< |
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154 | * Interrupts sourced from the L2 Cache Controller. |
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155 | * |
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156 | * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache |
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157 | * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR, |
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158 | * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts. |
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159 | * Consult the L2C documentation for information on these interrupts. |
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160 | * |
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161 | * * ECC interrupts in this group are edge triggered. |
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162 | * * Other interrupts in this group are level triggered. |
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163 | */ |
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164 | |
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165 | ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71, |
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166 | /*!< |
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167 | * Interrupts sourced from the SDRAM Controller. |
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168 | * * All interrupts in this group are level triggered. |
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169 | */ |
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170 | |
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171 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */ |
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172 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */ |
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173 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */ |
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174 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */ |
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175 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */ |
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176 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */ |
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177 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */ |
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178 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */ |
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179 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */ |
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180 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */ |
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181 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */ |
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182 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */ |
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183 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */ |
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184 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */ |
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185 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */ |
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186 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */ |
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187 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */ |
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188 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */ |
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189 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */ |
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190 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */ |
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191 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */ |
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192 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */ |
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193 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */ |
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194 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */ |
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195 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */ |
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196 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */ |
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197 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */ |
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198 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */ |
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199 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */ |
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200 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */ |
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201 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */ |
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202 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */ |
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203 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */ |
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204 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */ |
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205 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */ |
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206 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */ |
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207 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */ |
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208 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */ |
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209 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */ |
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210 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */ |
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211 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */ |
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212 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */ |
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213 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */ |
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214 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */ |
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215 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */ |
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216 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */ |
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217 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */ |
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218 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */ |
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219 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */ |
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220 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */ |
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221 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */ |
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222 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */ |
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223 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */ |
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224 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */ |
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225 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */ |
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226 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */ |
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227 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */ |
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228 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */ |
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229 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */ |
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230 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */ |
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231 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */ |
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232 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */ |
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233 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */ |
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234 | ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135, |
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235 | /*!< |
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236 | * Interrupt request from the FPGA logic, 0 - 63. |
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237 | * * Trigger type depends on the implementation in the FPGA. |
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238 | */ |
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239 | |
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240 | ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */ |
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241 | ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */ |
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242 | ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */ |
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243 | ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */ |
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244 | ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */ |
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245 | ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */ |
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246 | ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */ |
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247 | ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */ |
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248 | ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */ |
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249 | ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */ |
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250 | ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146, |
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251 | /*!< |
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252 | * Interrupts sourced from the DMA Controller. |
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253 | * * All interrupts in this group are level triggered. |
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254 | */ |
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255 | |
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256 | ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */ |
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257 | ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */ |
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258 | ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */ |
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259 | ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */ |
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260 | ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151, |
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261 | /*!< |
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262 | * Interrupts sourced from the Ethernet MAC 0 (EMAC0). |
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263 | * * All interrupts in this group are level triggered. |
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264 | */ |
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265 | |
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266 | ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */ |
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267 | ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */ |
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268 | ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */ |
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269 | ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */ |
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270 | ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156, |
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271 | /*!< |
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272 | * Interrupts sourced from the Ethernet MAC 1 (EMAC1). |
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273 | * * All interrupts in this group are level triggered. |
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274 | */ |
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275 | |
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276 | ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */ |
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277 | ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */ |
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278 | ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159, |
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279 | /*!< |
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280 | * Interrupts sourced from the USB OTG 0. |
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281 | * * All interrupts in this group are level triggered. |
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282 | */ |
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283 | |
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284 | ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */ |
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285 | ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */ |
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286 | ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162, |
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287 | /*!< |
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288 | * Interrupts sourced from the USB OTG 1. |
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289 | * * All interrupts in this group are level triggered. |
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290 | */ |
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291 | |
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292 | ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */ |
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293 | ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */ |
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294 | ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */ |
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295 | ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166, |
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296 | /*!< |
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297 | * Interrupts sourced from the CAN Controller 0. |
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298 | * * All interrupts in this group are level triggered. |
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299 | */ |
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300 | |
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301 | ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */ |
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302 | ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */ |
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303 | ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */ |
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304 | ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170, |
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305 | /*!< |
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306 | * Interrupts sourced from the CAN Controller 1. |
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307 | * * All interrupts in this group are level triggered. |
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308 | */ |
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309 | |
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310 | ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */ |
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311 | ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */ |
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312 | ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */ |
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313 | ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */ |
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314 | ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175, |
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315 | /*!< |
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316 | * Interrupts sourced from the SDMMC Controller. |
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317 | * * All interrupts in this group are level triggered. |
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318 | */ |
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319 | |
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320 | ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */ |
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321 | ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */ |
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322 | ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */ |
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323 | ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */ |
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324 | ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */ |
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325 | ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */ |
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326 | ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182, |
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327 | /*!< |
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328 | * Interrupts sourced from the NAND Controller. |
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329 | * * All interrupts in this group are level triggered. |
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330 | */ |
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331 | |
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332 | ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */ |
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333 | ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */ |
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334 | ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185, |
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335 | /*!< |
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336 | * Interrupts sourced from the QSPI Controller. |
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337 | * * All interrupts in this group are level triggered. |
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338 | */ |
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339 | |
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340 | ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */ |
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341 | ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */ |
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342 | ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */ |
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343 | ALT_INT_INTERRUPT_SPI3_IRQ = 189, |
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344 | /*!< |
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345 | * Interrupts sourced from the SPI Controllers 0 - 3. |
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346 | * * All interrupts in this group are level triggered. |
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347 | */ |
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348 | |
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349 | ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */ |
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350 | ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */ |
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351 | ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */ |
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352 | ALT_INT_INTERRUPT_I2C3_IRQ = 193, |
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353 | /*!< |
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354 | * Interrupts sourced from the I2C Controllers 0 - 3. |
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355 | * * All interrupts in this group are level triggered. |
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356 | */ |
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357 | |
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358 | ALT_INT_INTERRUPT_UART0 = 194, /*!< # */ |
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359 | ALT_INT_INTERRUPT_UART1 = 195, |
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360 | /*!< |
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361 | * Interrupts sourced from the UARTs 0 - 1. |
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362 | * * All interrupts in this group are level triggered. |
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363 | */ |
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364 | |
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365 | ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */ |
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366 | ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */ |
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367 | ALT_INT_INTERRUPT_GPIO2 = 198, |
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368 | /*!< |
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369 | * Interrupts sourced from the GPIO 0 - 2. |
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370 | * * All interrupts in this group are level triggered. |
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371 | */ |
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372 | |
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373 | ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */ |
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374 | ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */ |
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375 | ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */ |
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376 | ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202, |
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377 | /*!< |
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378 | * Interrupts sourced from the Timer controllers. |
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379 | * * All interrupts in this group are level triggered. |
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380 | */ |
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381 | |
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382 | ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */ |
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383 | ALT_INT_INTERRUPT_WDOG1_IRQ = 204, |
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384 | /*!< |
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385 | * Interrupts sourced from the Watchdog Timers 0 - 1. |
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386 | * * All interrupts in this group are level triggered. |
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387 | */ |
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388 | |
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389 | ALT_INT_INTERRUPT_CLKMGR_IRQ = 205, |
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390 | /*!< |
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391 | * Interrupts sourced from the Clock Manager. |
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392 | * * All interrupts in this group are level triggered. |
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393 | */ |
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394 | |
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395 | ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206, |
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396 | /*!< |
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397 | * Interrupts sourced from the Clock Manager MPU Wakeup. |
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398 | * * All interrupts in this group are level triggered. |
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399 | */ |
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400 | |
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401 | ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207, |
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402 | /*!< |
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403 | * Interrupts sourced from the FPGA Manager. |
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404 | * * All interrupts in this group are level triggered. |
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405 | */ |
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406 | |
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407 | ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */ |
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408 | ALT_INT_INTERRUPT_NCTIIRQ1 = 209, |
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409 | /*!< |
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410 | * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI. |
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411 | * * All interrupts in this group are level triggered. |
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412 | */ |
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413 | |
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414 | ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */ |
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415 | ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211 |
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416 | /*!< |
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417 | * Interrupts sourced from the On-chip RAM. |
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418 | * * All interrupts in this group are level triggered. |
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419 | */ |
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420 | |
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421 | } ALT_INT_INTERRUPT_t; |
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422 | |
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423 | /*! |
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424 | * This is the CPU target type. It is used to specify a set of CPUs on the |
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425 | * system. If only bit 0 is set then it specifies a set of CPUs containing |
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426 | * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit |
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427 | * up to the number of CPUs on the system. |
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428 | */ |
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429 | typedef uint32_t alt_int_cpu_target_t; |
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430 | |
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431 | /*! |
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432 | * This type definition enumerates all the interrupt trigger types. |
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433 | */ |
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434 | typedef enum ALT_INT_TRIGGER_e |
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435 | { |
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436 | /*! |
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437 | * Edge triggered interrupt. This applies to Private Peripheral Interrupts |
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438 | * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs |
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439 | * 16 - 1019. |
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440 | */ |
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441 | ALT_INT_TRIGGER_EDGE, |
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442 | |
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443 | /*! |
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444 | * Level triggered interrupt. This applies to Private Peripheral |
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445 | * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with |
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446 | * interrupt IDs 16 - 1019. |
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447 | */ |
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448 | ALT_INT_TRIGGER_LEVEL, |
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449 | |
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450 | /*! |
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451 | * Software triggered interrupt. This applies to Software Generated |
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452 | * Interrupts (SGI) only, with interrupt IDs 0 - 15. |
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453 | */ |
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454 | ALT_INT_TRIGGER_SOFTWARE, |
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455 | |
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456 | /*! |
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457 | * All triggering types except for those in the Shared Peripheral Interrupts |
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458 | * (SPI) F2S FPGA family interrupts can be determined by the system |
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459 | * automatically. In all functions which ask for the triggering type, the |
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460 | * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger |
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461 | * type for all non F2S interrupt types. |
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462 | */ |
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463 | ALT_INT_TRIGGER_AUTODETECT, |
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464 | |
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465 | /*! |
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466 | * The interrupt triggering information is not applicable. This is possibly |
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467 | * due to querying an invalid interrupt identifier. |
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468 | */ |
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469 | ALT_INT_TRIGGER_NA |
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470 | } |
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471 | ALT_INT_TRIGGER_t; |
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472 | |
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473 | /*! |
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474 | * This type definition enumerates all the target list filter options. This is |
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475 | * used by the trigger Software Generated Interrupt (SGI) feature to issue a |
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476 | * SGI to the specified processor(s) in the system. Depending on the target |
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477 | * list filter and the target list, interrupts can be routed to any |
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478 | * combinations of CPUs. |
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479 | */ |
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480 | typedef enum ALT_INT_SGI_TARGET_e |
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481 | { |
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482 | /*! |
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483 | * This filter list uses the target list parameter to specify which CPUs |
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484 | * to send the interrupt to. If target list is 0, no interrupts are sent. |
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485 | */ |
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486 | ALT_INT_SGI_TARGET_LIST, |
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487 | |
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488 | /*! |
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489 | * This filter list sends the interrupt all CPUs except the current CPU. |
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490 | * The target list parameter is ignored. |
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491 | */ |
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492 | ALT_INT_SGI_TARGET_ALL_EXCL_SENDER, |
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493 | |
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494 | /*! |
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495 | * This filter list sends the interrupt to the current CPU only. The |
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496 | * target list parameter is ignored. |
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497 | */ |
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498 | ALT_INT_SGI_TARGET_SENDER_ONLY |
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499 | } |
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500 | ALT_INT_SGI_TARGET_t; |
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501 | |
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502 | /*! |
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503 | * Extracts the CPUID field from the ICCIAR register. |
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504 | */ |
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505 | #define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7) |
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506 | |
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507 | /*! |
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508 | * Extracts the ACKINTID field from the ICCIAR register. |
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509 | */ |
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510 | #define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF) |
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511 | |
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512 | /*! |
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513 | * The callback to use when an interrupt needs to be serviced. |
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514 | * |
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515 | * \param icciar The Interrupt Controller CPU Interrupt |
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516 | * Acknowledgement Register value (ICCIAR) value |
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517 | * corresponding to the current interrupt. |
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518 | * |
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519 | * \param context The user provided context. |
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520 | */ |
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521 | typedef void (*alt_int_callback_t)(uint32_t icciar, void * context); |
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522 | |
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523 | /*! |
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524 | * @} |
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525 | */ |
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526 | |
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527 | #ifdef __cplusplus |
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528 | } |
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529 | #endif |
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530 | |
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531 | #endif /* __ALT_INT_COMMON_H__ */ |
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