source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_interrupt_common.h @ 0b03ca39

4.115
Last change on this file since 0b03ca39 was 0b03ca39, checked in by Ralf Kirchner <ralf.kirchner@…>, on 02/14/14 at 14:00:31

bsp/altera-cyclone-v: Add Alteras hwlib

Add files from Alteras hwlib

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1/******************************************************************************
2*
3* Copyright 2013 Altera Corporation. All Rights Reserved.
4*
5* Redistribution and use in source and binary forms, with or without
6* modification, are permitted provided that the following conditions are met:
7*
8* 1. Redistributions of source code must retain the above copyright notice,
9* this list of conditions and the following disclaimer.
10*
11* 2. Redistributions in binary form must reproduce the above copyright notice,
12* this list of conditions and the following disclaimer in the documentation
13* and/or other materials provided with the distribution.
14*
15* 3. The name of the author may not be used to endorse or promote products
16* derived from this software without specific prior written permission.
17*
18* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
19* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
21* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
23* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27* OF SUCH DAMAGE.
28*
29******************************************************************************/
30
31#ifndef __ALT_INT_COMMON_H__
32#define __ALT_INT_COMMON_H__
33
34#include "hwlib.h"
35#include <stdbool.h>
36#include <stddef.h>
37
38#ifdef __cplusplus
39extern "C"
40{
41#endif
42
43/*!
44 * \addtogroup INT_COMMON Interrupt Controller Common Definitions
45 *
46 * This module contains the definitions common to the Interrupt Controller
47 * Low-Level API and Interrupt Controller Manager Interface.
48 *
49 * @{
50 */
51
52/*!
53 * This type definition enumerates all the interrupt identification types.
54 */
55typedef enum ALT_INT_INTERRUPT_e
56{
57    ALT_INT_INTERRUPT_SGI0  =  0, /*!< # */
58    ALT_INT_INTERRUPT_SGI1  =  1, /*!< # */
59    ALT_INT_INTERRUPT_SGI2  =  2, /*!< # */
60    ALT_INT_INTERRUPT_SGI3  =  3, /*!< # */
61    ALT_INT_INTERRUPT_SGI4  =  4, /*!< # */
62    ALT_INT_INTERRUPT_SGI5  =  5, /*!< # */
63    ALT_INT_INTERRUPT_SGI6  =  6, /*!< # */
64    ALT_INT_INTERRUPT_SGI7  =  7, /*!< # */
65    ALT_INT_INTERRUPT_SGI8  =  8, /*!< # */
66    ALT_INT_INTERRUPT_SGI9  =  9, /*!< # */
67    ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
68    ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
69    ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
70    ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
71    ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
72    ALT_INT_INTERRUPT_SGI15 = 15,
73    /*!<
74     * Software Generated Interrupts (SGI), 0 - 15.
75     *  * All interrupts in this group are software triggered.
76     */
77
78    ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL   = 27, /*!< # */
79    ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE  = 29, /*!< # */
80    ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
81    /*!<
82     * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
83     * private timer, and watchdog timer.
84     *  * All interrupts in this group are edge triggered.
85     */
86
87    ALT_INT_INTERRUPT_CPU0_PARITYFAIL         = 32, /*!< # */
88    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC    = 33, /*!< # */
89    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB     = 34, /*!< # */
90    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG   = 35, /*!< # */
91    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA  = 36, /*!< # */
92    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB     = 37, /*!< # */
93    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
94    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG   = 39, /*!< # */
95    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA  = 40, /*!< # */
96    ALT_INT_INTERRUPT_CPU0_DEFLAGS0           = 41, /*!< # */
97    ALT_INT_INTERRUPT_CPU0_DEFLAGS1           = 42, /*!< # */
98    ALT_INT_INTERRUPT_CPU0_DEFLAGS2           = 43, /*!< # */
99    ALT_INT_INTERRUPT_CPU0_DEFLAGS3           = 44, /*!< # */
100    ALT_INT_INTERRUPT_CPU0_DEFLAGS4           = 45, /*!< # */
101    ALT_INT_INTERRUPT_CPU0_DEFLAGS5           = 46, /*!< # */
102    ALT_INT_INTERRUPT_CPU0_DEFLAGS6           = 47,
103    /*!<
104     * Interrupts sourced from CPU0.
105     *
106     * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
107     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
108     * for CPU0.
109     *
110     *  * PARITYFAIL interrupts in this group are edge triggered.
111     *  * DEFFLAGS interrupts in this group are level triggered.
112     */
113
114    ALT_INT_INTERRUPT_CPU1_PARITYFAIL         = 48, /*!< # */
115    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC    = 49, /*!< # */
116    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB     = 50, /*!< # */
117    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG   = 51, /*!< # */
118    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA  = 52, /*!< # */
119    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB     = 53, /*!< # */
120    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
121    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG   = 55, /*!< # */
122    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA  = 56, /*!< # */
123    ALT_INT_INTERRUPT_CPU1_DEFLAGS0           = 57, /*!< # */
124    ALT_INT_INTERRUPT_CPU1_DEFLAGS1           = 58, /*!< # */
125    ALT_INT_INTERRUPT_CPU1_DEFLAGS2           = 59, /*!< # */
126    ALT_INT_INTERRUPT_CPU1_DEFLAGS3           = 60, /*!< # */
127    ALT_INT_INTERRUPT_CPU1_DEFLAGS4           = 61, /*!< # */
128    ALT_INT_INTERRUPT_CPU1_DEFLAGS5           = 62, /*!< # */
129    ALT_INT_INTERRUPT_CPU1_DEFLAGS6           = 63,
130    /*!<
131     * Interrupts sourced from CPU1.
132     *
133     * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
134     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
135     * for CPU1.
136     *
137     *  * PARITYFAIL interrupts in this group are edge triggered.
138     *  * DEFFLAGS interrupts in this group are level triggered.
139     */
140   
141    ALT_INT_INTERRUPT_SCU_PARITYFAIL0 =  64, /*!< # */
142    ALT_INT_INTERRUPT_SCU_PARITYFAIL1 =  65, /*!< # */
143    ALT_INT_INTERRUPT_SCU_EV_ABORT    =  66,
144    /*!<
145     * Interrupts sourced from the Snoop Control Unit (SCU).
146     *  * All interrupts in this group are edge triggered.
147     */
148   
149    ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ     = 67, /*!< # */
150    ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ   = 68, /*!< # */
151    ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
152    ALT_INT_INTERRUPT_L2_COMBINED_IRQ        = 70,
153    /*!<
154     * Interrupts sourced from the L2 Cache Controller.
155     *
156     * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
157     * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
158     * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
159     * Consult the L2C documentation for information on these interrupts.
160     *
161     *  * ECC interrupts in this group are edge triggered.
162     *  * Other interrupts in this group are level triggered.
163     */
164
165    ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ =  71,
166    /*!<
167     * Interrupts sourced from the SDRAM Controller.
168     *  * All interrupts in this group are level triggered.
169     */
170
171    ALT_INT_INTERRUPT_F2S_FPGA_IRQ0  =  72, /*!< # */
172    ALT_INT_INTERRUPT_F2S_FPGA_IRQ1  =  73, /*!< # */
173    ALT_INT_INTERRUPT_F2S_FPGA_IRQ2  =  74, /*!< # */
174    ALT_INT_INTERRUPT_F2S_FPGA_IRQ3  =  75, /*!< # */
175    ALT_INT_INTERRUPT_F2S_FPGA_IRQ4  =  76, /*!< # */
176    ALT_INT_INTERRUPT_F2S_FPGA_IRQ5  =  77, /*!< # */
177    ALT_INT_INTERRUPT_F2S_FPGA_IRQ6  =  78, /*!< # */
178    ALT_INT_INTERRUPT_F2S_FPGA_IRQ7  =  79, /*!< # */
179    ALT_INT_INTERRUPT_F2S_FPGA_IRQ8  =  80, /*!< # */
180    ALT_INT_INTERRUPT_F2S_FPGA_IRQ9  =  81, /*!< # */
181    ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 =  82, /*!< # */
182    ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 =  83, /*!< # */
183    ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 =  84, /*!< # */
184    ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 =  85, /*!< # */
185    ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 =  86, /*!< # */
186    ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 =  87, /*!< # */
187    ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 =  88, /*!< # */
188    ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 =  89, /*!< # */
189    ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 =  90, /*!< # */
190    ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 =  91, /*!< # */
191    ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 =  92, /*!< # */
192    ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 =  93, /*!< # */
193    ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 =  94, /*!< # */
194    ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 =  95, /*!< # */
195    ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 =  96, /*!< # */
196    ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 =  97, /*!< # */
197    ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 =  98, /*!< # */
198    ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 =  99, /*!< # */
199    ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
200    ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
201    ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
202    ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
203    ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
204    ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
205    ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
206    ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
207    ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
208    ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
209    ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
210    ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
211    ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
212    ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
213    ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
214    ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
215    ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
216    ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
217    ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
218    ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
219    ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
220    ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
221    ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
222    ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
223    ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
224    ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
225    ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
226    ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
227    ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
228    ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
229    ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
230    ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
231    ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
232    ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
233    ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
234    ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
235    /*!<
236     * Interrupt request from the FPGA logic, 0 - 63.
237     *  * Trigger type depends on the implementation in the FPGA.
238     */
239
240    ALT_INT_INTERRUPT_DMA_IRQ0                = 136, /*!< # */
241    ALT_INT_INTERRUPT_DMA_IRQ1                = 137, /*!< # */
242    ALT_INT_INTERRUPT_DMA_IRQ2                = 138, /*!< # */
243    ALT_INT_INTERRUPT_DMA_IRQ3                = 139, /*!< # */
244    ALT_INT_INTERRUPT_DMA_IRQ4                = 140, /*!< # */
245    ALT_INT_INTERRUPT_DMA_IRQ5                = 141, /*!< # */
246    ALT_INT_INTERRUPT_DMA_IRQ6                = 142, /*!< # */
247    ALT_INT_INTERRUPT_DMA_IRQ7                = 143, /*!< # */
248    ALT_INT_INTERRUPT_DMA_IRQ_ABORT           = 144, /*!< # */
249    ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ   = 145, /*!< # */
250    ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
251    /*!<
252     * Interrupts sourced from the DMA Controller.
253     *  * All interrupts in this group are level triggered.
254     */
255
256    ALT_INT_INTERRUPT_EMAC0_IRQ                    = 147, /*!< # */
257    ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ   = 148, /*!< # */
258    ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
259    ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ   = 150, /*!< # */
260    ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
261    /*!<
262     * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
263     *  * All interrupts in this group are level triggered.
264     */
265
266    ALT_INT_INTERRUPT_EMAC1_IRQ                    = 152, /*!< # */
267    ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ   = 153, /*!< # */
268    ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
269    ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ   = 155, /*!< # */
270    ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
271    /*!<
272     * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
273     *  * All interrupts in this group are level triggered.
274     */
275
276    ALT_INT_INTERRUPT_USB0_IRQ             = 157, /*!< # */
277    ALT_INT_INTERRUPT_USB0_ECC_CORRECTED   = 158, /*!< # */
278    ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
279    /*!<
280     * Interrupts sourced from the USB OTG 0.
281     *  * All interrupts in this group are level triggered.
282     */
283
284    ALT_INT_INTERRUPT_USB1_IRQ             = 160, /*!< # */
285    ALT_INT_INTERRUPT_USB1_ECC_CORRECTED   = 161, /*!< # */
286    ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
287    /*!<
288     * Interrupts sourced from the USB OTG 1.
289     *  * All interrupts in this group are level triggered.
290     */
291
292    ALT_INT_INTERRUPT_CAN0_STS_IRQ             = 163, /*!< # */
293    ALT_INT_INTERRUPT_CAN0_MO_IRQ              = 164, /*!< # */
294    ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ   = 165, /*!< # */
295    ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
296    /*!<
297     * Interrupts sourced from the CAN Controller 0.
298     *  * All interrupts in this group are level triggered.
299     */
300
301    ALT_INT_INTERRUPT_CAN1_STS_IRQ             = 167, /*!< # */
302    ALT_INT_INTERRUPT_CAN1_MO_IRQ              = 168, /*!< # */
303    ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ   = 169, /*!< # */
304    ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
305    /*!<
306     * Interrupts sourced from the CAN Controller 1.
307     *  * All interrupts in this group are level triggered.
308     */
309
310    ALT_INT_INTERRUPT_SDMMC_IRQ                   = 171, /*!< # */
311    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED   = 172, /*!< # */
312    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
313    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED   = 174, /*!< # */
314    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
315    /*!<
316     * Interrupts sourced from the SDMMC Controller.
317     *  * All interrupts in this group are level triggered.
318     */
319
320    ALT_INT_INTERRUPT_NAND_IRQ                  = 176, /*!< # */
321    ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ   = 177, /*!< # */
322    ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
323    ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ   = 179, /*!< # */
324    ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
325    ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ   = 181, /*!< # */
326    ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
327    /*!<
328     * Interrupts sourced from the NAND Controller.
329     *  * All interrupts in this group are level triggered.
330     */
331
332    ALT_INT_INTERRUPT_QSPI_IRQ                 = 183, /*!< # */
333    ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ   = 184, /*!< # */
334    ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
335    /*!<
336     * Interrupts sourced from the QSPI Controller.
337     *  * All interrupts in this group are level triggered.
338     */
339
340    ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
341    ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
342    ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
343    ALT_INT_INTERRUPT_SPI3_IRQ = 189,
344    /*!<
345     * Interrupts sourced from the SPI Controllers 0 - 3.
346     *  * All interrupts in this group are level triggered.
347     */
348
349    ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
350    ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
351    ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
352    ALT_INT_INTERRUPT_I2C3_IRQ = 193,
353    /*!<
354     * Interrupts sourced from the I2C Controllers 0 - 3.
355     *  * All interrupts in this group are level triggered.
356     */
357
358    ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
359    ALT_INT_INTERRUPT_UART1 = 195,
360    /*!<
361     * Interrupts sourced from the UARTs 0 - 1.
362     *  * All interrupts in this group are level triggered.
363     */
364
365    ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
366    ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
367    ALT_INT_INTERRUPT_GPIO2 = 198,
368    /*!<
369     * Interrupts sourced from the GPIO 0 - 2.
370     *  * All interrupts in this group are level triggered.
371     */
372   
373    ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
374    ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
375    ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
376    ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
377    /*!<
378     * Interrupts sourced from the Timer controllers.
379     *  * All interrupts in this group are level triggered.
380     */
381
382    ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
383    ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
384    /*!<
385     * Interrupts sourced from the Watchdog Timers 0 - 1.
386     *  * All interrupts in this group are level triggered.
387     */
388
389    ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
390    /*!<
391     * Interrupts sourced from the Clock Manager.
392     *  * All interrupts in this group are level triggered.
393     */
394
395    ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
396    /*!<
397     * Interrupts sourced from the Clock Manager MPU Wakeup.
398     *  * All interrupts in this group are level triggered.
399     */
400
401    ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
402    /*!<
403     * Interrupts sourced from the FPGA Manager.
404     *  * All interrupts in this group are level triggered.
405     */
406
407    ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
408    ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
409    /*!<
410     * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
411     *  * All interrupts in this group are level triggered.
412     */
413
414    ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ   = 210, /*!< # */
415    ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
416    /*!<
417     * Interrupts sourced from the On-chip RAM.
418     *  * All interrupts in this group are level triggered.
419     */
420
421} ALT_INT_INTERRUPT_t;
422
423/*!
424 * This is the CPU target type. It is used to specify a set of CPUs on the
425 * system. If only bit 0 is set then it specifies a set of CPUs containing
426 * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
427 * up to the number of CPUs on the system.
428 */
429typedef uint32_t alt_int_cpu_target_t;
430
431/*!
432 * This type definition enumerates all the interrupt trigger types.
433 */
434typedef enum ALT_INT_TRIGGER_e
435{
436    /*!
437     * Edge triggered interrupt. This applies to Private Peripheral Interrupts
438     * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
439     * 16 - 1019.
440     */
441    ALT_INT_TRIGGER_EDGE,
442
443    /*!
444     * Level triggered interrupt. This applies to Private Peripheral
445     * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
446     * interrupt IDs 16 - 1019.
447     */
448    ALT_INT_TRIGGER_LEVEL,
449
450    /*!
451     * Software triggered interrupt. This applies to Software Generated
452     * Interrupts (SGI) only, with interrupt IDs 0 - 15.
453     */
454    ALT_INT_TRIGGER_SOFTWARE,
455
456    /*!
457     * All triggering types except for those in the Shared Peripheral Interrupts
458     * (SPI) F2S FPGA family interrupts can be determined by the system
459     * automatically. In all functions which ask for the triggering type, the
460     * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
461     * type for all non F2S interrupt types.
462     */
463    ALT_INT_TRIGGER_AUTODETECT,
464
465    /*!
466     * The interrupt triggering information is not applicable. This is possibly
467     * due to querying an invalid interrupt identifier.
468     */
469    ALT_INT_TRIGGER_NA
470}
471ALT_INT_TRIGGER_t;
472
473/*!
474 * This type definition enumerates all the target list filter options. This is
475 * used by the trigger Software Generated Interrupt (SGI) feature to issue a
476 * SGI to the specified processor(s) in the system. Depending on the target
477 * list filter and the target list, interrupts can be routed to any
478 * combinations of CPUs.
479 */
480typedef enum ALT_INT_SGI_TARGET_e
481{
482    /*!
483     * This filter list uses the target list parameter to specify which CPUs
484     * to send the interrupt to. If target list is 0, no interrupts are sent.
485     */
486    ALT_INT_SGI_TARGET_LIST,
487
488    /*!
489     * This filter list sends the interrupt all CPUs except the current CPU.
490     * The target list parameter is ignored.
491     */
492    ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
493
494    /*!
495     * This filter list sends the interrupt to the current CPU only. The
496     * target list parameter is ignored.
497     */
498    ALT_INT_SGI_TARGET_SENDER_ONLY
499}
500ALT_INT_SGI_TARGET_t;
501
502/*!
503 * Extracts the CPUID field from the ICCIAR register.
504 */
505#define ALT_INT_ICCIAR_CPUID_GET(icciar)    ((icciar >> 10) & 0x7)
506
507/*!
508 * Extracts the ACKINTID field from the ICCIAR register.
509 */
510#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
511
512/*!
513 * The callback to use when an interrupt needs to be serviced.
514 *
515 * \param       icciar          The Interrupt Controller CPU Interrupt
516 *                              Acknowledgement Register value (ICCIAR) value
517 *                              corresponding to the current interrupt.
518 *
519 * \param       context         The user provided context.
520 */
521typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
522
523/*!
524 * @}
525 */
526
527#ifdef __cplusplus
528}
529#endif
530
531#endif /* __ALT_INT_COMMON_H__ */
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