[76386c1] | 1 | /****************************************************************************** |
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| 2 | * |
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| 3 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions are met: |
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| 7 | * |
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| 8 | * 1. Redistributions of source code must retain the above copyright notice, |
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| 9 | * this list of conditions and the following disclaimer. |
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| 10 | * |
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| 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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| 12 | * this list of conditions and the following disclaimer in the documentation |
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| 13 | * and/or other materials provided with the distribution. |
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| 14 | * |
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| 15 | * 3. The name of the author may not be used to endorse or promote products |
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| 16 | * derived from this software without specific prior written permission. |
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| 17 | * |
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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| 21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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| 22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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| 23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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| 26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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| 27 | * OF SUCH DAMAGE. |
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| 28 | * |
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| 29 | ******************************************************************************/ |
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| 30 | |
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| 31 | #ifndef __ALT_DMA_PROGRAM_H__ |
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| 32 | #define __ALT_DMA_PROGRAM_H__ |
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| 33 | |
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| 34 | #include "hwlib.h" |
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| 35 | #include "alt_dma_common.h" |
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| 36 | |
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| 37 | #ifdef __cplusplus |
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| 38 | extern "C" |
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| 39 | { |
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| 40 | #endif /* __cplusplus */ |
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| 41 | |
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| 42 | /*! |
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| 43 | * \addtogroup ALT_DMA_PRG DMA Controller Programming API |
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| 44 | * |
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| 45 | * This API provides functions for dynamically defining and assembling microcode |
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| 46 | * programs for execution on the DMA controller. |
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| 47 | * |
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| 48 | * The microcode program assembly API provides users with the ability to develop |
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| 49 | * highly optimized and tailored algorithms for data transfer between SoC FPGA |
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| 50 | * IP blocks and/or system memory. |
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| 51 | * |
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| 52 | * The same microcode program assembly facilities are also used to implement the |
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| 53 | * functions found in the HWLIB Common DMA Operations functional API. |
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| 54 | * |
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| 55 | * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA |
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| 56 | * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated |
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| 57 | * from used specified system memory. Once a microcode program has been |
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| 58 | * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA |
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| 59 | * channel thread. The microcode program may be rerun on any DMA channel thread |
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| 60 | * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t |
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| 61 | * containing the program is maintained. |
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| 62 | * |
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| 63 | * @{ |
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| 64 | */ |
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| 65 | |
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| 66 | /*! |
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| 67 | * This preprocessor declares the DMA channel thread microcode instruction |
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| 68 | * cache line width in bytes. It is recommended that the program buffers be |
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| 69 | * sized to a multiple of the cache line size. This will allow for the most |
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| 70 | * efficient microcode speed and space utilization. |
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| 71 | */ |
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| 72 | #define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32) |
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| 73 | |
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| 74 | /*! |
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| 75 | * This preprocessor declares the DMA channel thread microcode instruction |
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| 76 | * cache line count. Thus the total size of the cache is the cache line size |
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| 77 | * multipled by the cache line count. Programs larger than the cache size risk |
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| 78 | * having a cache miss while executing. |
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| 79 | */ |
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| 80 | #define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16) |
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| 81 | |
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| 82 | /*! |
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| 83 | * This preprocessor definition determines the size of the program buffer |
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| 84 | * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate |
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| 85 | * size for most DMA microcode programs. If calls within this API are |
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| 86 | * reporting out of memory response codes, consider increasing the provisioned |
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| 87 | * program buffersize. |
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| 88 | * |
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| 89 | * To specify another DMA microcode program buffer size, redefine the macro |
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| 90 | * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in |
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| 91 | * your Makefile. It is recommended that the size be a multiple of the |
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| 92 | * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for |
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| 93 | * more information. The largest supported buffer size is 65536 bytes. |
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| 94 | */ |
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| 95 | #ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE |
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| 96 | #define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT) |
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| 97 | #endif |
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| 98 | |
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| 99 | /*! |
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| 100 | * This type defines the structure used to assemble and contain a microcode |
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| 101 | * program which can be executed by the DMA controller. The internal members |
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| 102 | * are undocumented and should not be altered outside of this API. |
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| 103 | */ |
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| 104 | typedef struct ALT_DMA_PROGRAM_s |
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| 105 | { |
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| 106 | uint32_t flag; |
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| 107 | |
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| 108 | uint16_t buffer_start; |
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| 109 | uint16_t code_size; |
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| 110 | |
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| 111 | uint16_t loop0; |
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| 112 | uint16_t loop1; |
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| 113 | |
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| 114 | uint16_t sar; |
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| 115 | uint16_t dar; |
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| 116 | |
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| 117 | /* |
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| 118 | * Add a little extra space so that regardless of where this structure |
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| 119 | * sits in memory, a suitable start address can be aligned to the cache |
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| 120 | * line stride while providing the requested buffer space. |
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| 121 | */ |
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| 122 | uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE + |
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| 123 | ALT_DMA_PROGRAM_CACHE_LINE_SIZE]; |
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| 124 | } |
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| 125 | ALT_DMA_PROGRAM_t; |
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| 126 | |
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| 127 | /*! |
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| 128 | * This type definition enumerates the DMA controller register names for use in |
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| 129 | * microcode program definition. |
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| 130 | */ |
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| 131 | typedef enum ALT_DMA_PROGRAM_REG_e |
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| 132 | { |
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| 133 | /*! Source Address Register */ |
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| 134 | ALT_DMA_PROGRAM_REG_SAR = 0x0, |
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| 135 | |
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| 136 | /*! Destination Address Register */ |
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| 137 | ALT_DMA_PROGRAM_REG_DAR = 0x2, |
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| 138 | |
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| 139 | /*! Channel Control Register */ |
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| 140 | ALT_DMA_PROGRAM_REG_CCR = 0x1 |
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| 141 | } |
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| 142 | ALT_DMA_PROGRAM_REG_t; |
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| 143 | |
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| 144 | /*! |
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| 145 | * This type definition enumerates the instruction modifier options available |
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| 146 | * for use with selected DMA microcode instructions. |
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| 147 | * |
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| 148 | * The enumerations values are context dependent upon the instruction being |
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| 149 | * modified. |
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| 150 | * |
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| 151 | * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and |
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| 152 | * <b>DMASTP\<S|B></b> microcode instructions, the enumeration |
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| 153 | * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier |
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| 154 | * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b> |
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| 155 | * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies |
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| 156 | * that no modifier is present for instructions where use of <b>[S|B]</b> is |
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| 157 | * optional. |
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| 158 | * |
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| 159 | * For the <b>DMAWFP</b> microcode instruction, the enumerations |
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| 160 | * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or |
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| 161 | * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding |
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| 162 | * options <b>\<single|burst|periph></b>. |
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| 163 | */ |
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| 164 | typedef enum ALT_DMA_PROGRAM_INST_MOD_e |
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| 165 | { |
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| 166 | /*! |
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| 167 | * This DMA instruction modifier specifies that no special modifier is |
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| 168 | * added to the instruction. |
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| 169 | */ |
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| 170 | ALT_DMA_PROGRAM_INST_MOD_NONE, |
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| 171 | |
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| 172 | /*! |
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| 173 | * Depending on the DMA microcode instruction modified, this modifier |
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| 174 | * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a |
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| 175 | * <b>\<single|burst|periph></b>. |
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| 176 | */ |
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| 177 | ALT_DMA_PROGRAM_INST_MOD_SINGLE, |
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| 178 | |
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| 179 | /*! |
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| 180 | * Depending on the DMA microcode instruction modified, this modifier |
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| 181 | * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a |
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| 182 | * <b>\<single|burst|periph></b>. |
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| 183 | */ |
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| 184 | ALT_DMA_PROGRAM_INST_MOD_BURST, |
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| 185 | |
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| 186 | /*! |
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| 187 | * This DMA instruction modifier specifies a <b>\<periph></b> for a |
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| 188 | * <b>\<single|burst|periph></b>. |
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| 189 | */ |
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| 190 | ALT_DMA_PROGRAM_INST_MOD_PERIPH |
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| 191 | } |
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| 192 | ALT_DMA_PROGRAM_INST_MOD_t; |
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| 193 | |
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| 194 | /*! |
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| 195 | * This function initializes a system memory buffer for use as a DMA microcode |
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| 196 | * program buffer. This should be the first API call made on the program |
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| 197 | * buffer type. |
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| 198 | * |
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| 199 | * \param pgm |
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| 200 | * A pointer to a DMA program buffer structure. |
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| 201 | * |
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| 202 | * \retval ALT_E_SUCCESS The operation was successful. |
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| 203 | * \retval ALT_E_ERROR Details about error status code |
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| 204 | */ |
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| 205 | ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm); |
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| 206 | |
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| 207 | /*! |
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| 208 | * This function verifies that the DMA microcode program buffer is no longer |
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| 209 | * in use and performs any needed uninitialization steps. |
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| 210 | * |
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| 211 | * \param pgm |
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| 212 | * A pointer to a DMA program buffer structure. |
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| 213 | * |
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| 214 | * \retval ALT_E_SUCCESS The operation was successful. |
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| 215 | * \retval ALT_E_ERROR Details about error status code |
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| 216 | */ |
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| 217 | ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm); |
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| 218 | |
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| 219 | /*! |
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| 220 | * This function clears the existing DMA microcode program in the given |
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| 221 | * program buffer. |
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| 222 | * |
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| 223 | * \param pgm |
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| 224 | * A pointer to a DMA program buffer structure. |
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| 225 | * |
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| 226 | * \retval ALT_E_SUCCESS The operation was successful. |
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| 227 | * \retval ALT_E_ERROR Details about error status code. |
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| 228 | */ |
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| 229 | ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm); |
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| 230 | |
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| 231 | /*! |
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| 232 | * This function validate that the given DMA microcode program buffer contains |
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| 233 | * a well formed program. If caches are enabled, the program buffer contents |
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| 234 | * will be cleaned to RAM. |
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| 235 | * |
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| 236 | * \param pgm |
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| 237 | * A pointer to a DMA program buffer structure. |
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| 238 | * |
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| 239 | * \retval ALT_E_SUCCESS The given program is well formed. |
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| 240 | * \retval ALT_E_ERROR The given program is not well formed. |
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| 241 | * \retval ALT_E_TMO The cache operation timed out. |
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| 242 | */ |
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| 243 | ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm); |
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| 244 | |
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| 245 | /*! |
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| 246 | * This function reports the number bytes incremented for the register |
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| 247 | * specified. The purpose is to determine the progress of an ongoing DMA |
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| 248 | * transfer. |
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| 249 | * |
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| 250 | * It is implemented by calculating the difference of the programmed SAR or DAR |
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| 251 | * with the current channel SAR or DAR register value. |
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| 252 | * |
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| 253 | * \param pgm |
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| 254 | * A pointer to a DMA program buffer structure. |
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| 255 | * |
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| 256 | * \param channel |
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| 257 | * The channel that the program is running on. |
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| 258 | * |
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| 259 | * \param reg |
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| 260 | * Register to change the value for. Valid for only |
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| 261 | * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. |
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| 262 | * |
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| 263 | * \param current |
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| 264 | * The current snapshot value of the register read from the DMA |
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| 265 | * channel. |
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| 266 | * |
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| 267 | * \param progress |
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| 268 | * [out] A pointer to a memory location that will be used to store |
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| 269 | * the number of bytes transfered. |
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| 270 | * |
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| 271 | * \retval ALT_E_SUCCESS The operation was successful. |
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| 272 | * \retval ALT_E_ERROR Details about error status code. |
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| 273 | * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified |
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| 274 | * register is invalid, or the DMAMOV for the |
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| 275 | * specified register has not yet been assembled |
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| 276 | * in the current program buffer. |
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| 277 | */ |
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| 278 | ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm, |
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| 279 | ALT_DMA_PROGRAM_REG_t reg, |
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| 280 | uint32_t current, uint32_t * progress); |
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| 281 | |
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| 282 | /*! |
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| 283 | * This function updates a pre-existing DMAMOV value affecting the SAR or DAR |
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| 284 | * registers. This allows for pre-assembled programs that can be used on |
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| 285 | * different source and destination addresses. |
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| 286 | * |
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| 287 | * \param pgm |
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| 288 | * A pointer to a DMA program buffer structure. |
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| 289 | * |
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| 290 | * \param reg |
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| 291 | * Register to change the value for. Valid for only |
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| 292 | * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR. |
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| 293 | * |
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| 294 | * \param val |
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| 295 | * The value to update to. |
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| 296 | * |
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| 297 | * \retval ALT_E_SUCCESS The operation was successful. |
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| 298 | * \retval ALT_E_ERROR Details about error status code. |
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| 299 | * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV |
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| 300 | * for the specified register has not yet been |
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| 301 | * assembled in the current program buffer. |
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| 302 | */ |
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| 303 | ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm, |
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| 304 | ALT_DMA_PROGRAM_REG_t reg, uint32_t val); |
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| 305 | |
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| 306 | /*! |
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| 307 | */ |
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| 308 | |
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| 309 | /*! |
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| 310 | * Assembles a DMAADDH (Add Halfword) instruction into the microcode program |
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| 311 | * buffer. This instruction uses 3 bytes of buffer space. |
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| 312 | * |
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| 313 | * \param pgm |
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| 314 | * The DMA program buffer to contain the assembled instruction. |
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| 315 | * |
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| 316 | * \param addr_reg |
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| 317 | * The channel address register (ALT_DMA_PROGRAM_REG_DAR or |
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| 318 | * ALT_DMA_PROGRAM_REG_SAR) to add the value to. |
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| 319 | * |
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| 320 | * \param val |
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| 321 | * The 16-bit unsigned value to add to the channel address |
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| 322 | * register. |
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| 323 | * |
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| 324 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 325 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 326 | * \retval ALT_E_BAD_ARG Invalid channel register specified. |
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| 327 | */ |
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| 328 | // Assembler Syntax: DMAADDH <address_register>, <16-bit immediate> |
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| 329 | ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm, |
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| 330 | ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); |
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| 331 | |
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| 332 | /*! |
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| 333 | * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode |
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| 334 | * program buffer. This instruction uses 3 bytes of buffer space. |
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| 335 | * |
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| 336 | * \param pgm |
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| 337 | * The DMA programm buffer to contain the assembled instruction. |
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| 338 | * |
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| 339 | * \param addr_reg |
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| 340 | * The channel address register (ALT_DMA_PROGRAM_REG_DAR or |
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| 341 | * ALT_DMA_PROGRAM_REG_SAR) to add the value to. |
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| 342 | * |
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| 343 | * \param val |
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| 344 | * The 16-bit unsigned value to add to the channel address |
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| 345 | * register. |
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| 346 | * |
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| 347 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 348 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 349 | * \retval ALT_E_BAD_ARG Invalid channel register specified. |
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| 350 | */ |
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| 351 | // Assembler Syntax: DMAADNH <address_register>, <16-bit immediate> |
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| 352 | ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm, |
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| 353 | ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val); |
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| 354 | |
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| 355 | /*! |
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| 356 | * Assembles a DMAEND (End) instruction into the microcode program buffer. |
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| 357 | * This instruction uses 1 byte of buffer space. |
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| 358 | * |
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| 359 | * \param pgm |
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| 360 | * The DMA programm buffer to contain the assembled instruction. |
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| 361 | * |
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| 362 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 363 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 364 | */ |
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| 365 | // Assembler Syntax: DMAEND |
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| 366 | ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm); |
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| 367 | |
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| 368 | /*! |
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| 369 | * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode |
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| 370 | * program buffer. This instruction uses 2 bytes of buffer space. |
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| 371 | * |
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| 372 | * \param pgm |
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| 373 | * The DMA programm buffer to contain the assembled instruction. |
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| 374 | * |
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| 375 | * \param periph |
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| 376 | * The peripheral to flush. |
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| 377 | * |
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| 378 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 379 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 380 | * \retval ALT_E_BAD_ARG Invalid peripheral specified. |
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| 381 | */ |
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| 382 | // Assembler Syntax: DMAFLUSHP <peripheral> |
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| 383 | ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm, |
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| 384 | ALT_DMA_PERIPH_t periph); |
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| 385 | |
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| 386 | /*! |
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| 387 | * Assembles a DMAGO (Go) instruction into the microcode program buffer. This |
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| 388 | * instruction uses 6 bytes of buffer space. |
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| 389 | * |
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| 390 | * \param pgm |
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| 391 | * The DMA programm buffer to contain the assembled instruction. |
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| 392 | * |
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| 393 | * \param channel |
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| 394 | * The stopped channel to act upon. |
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| 395 | * |
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| 396 | * \param val |
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| 397 | * The value to write to the channel program counter register. |
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| 398 | * |
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| 399 | * \param sec |
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| 400 | * The security state for the operation. |
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| 401 | * |
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| 402 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 403 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 404 | * \retval ALT_E_BAD_ARG Invalid channel or security specified. |
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| 405 | */ |
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| 406 | // Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns] |
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| 407 | ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm, |
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| 408 | ALT_DMA_CHANNEL_t channel, uint32_t val, |
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| 409 | ALT_DMA_SECURITY_t sec); |
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| 410 | |
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| 411 | /*! |
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| 412 | * Assembles a DMAKILL (Kill) instruction into the microcode program buffer. |
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| 413 | * This instruction uses 1 byte of buffer space. |
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| 414 | * |
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| 415 | * \param pgm |
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| 416 | * The DMA programm buffer to contain the assembled instruction. |
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| 417 | * |
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| 418 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 419 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 420 | */ |
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| 421 | // Assembler Syntax: DMAKILL |
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| 422 | ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm); |
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| 423 | |
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| 424 | /*! |
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| 425 | * Assembles a DMALD (Load) instruction into the microcode program buffer. |
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| 426 | * This instruction uses 1 byte of buffer space. |
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| 427 | * |
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| 428 | * \param pgm |
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| 429 | * The DMA programm buffer to contain the assembled instruction. |
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| 430 | * |
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| 431 | * \param mod |
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| 432 | * The program instruction modifier for the type of transfer. |
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| 433 | * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and |
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| 434 | * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. |
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| 435 | * |
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| 436 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
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| 437 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
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| 438 | * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. |
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| 439 | */ |
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| 440 | // Assembler Syntax: DMALD[S|B] |
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| 441 | ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm, |
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| 442 | ALT_DMA_PROGRAM_INST_MOD_t mod); |
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| 443 | |
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| 444 | /*! |
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| 445 | * Assembles a DMALDP (Load and notify Peripheral) instruction into the |
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| 446 | * microcode program buffer. This instruction uses 2 bytes of buffer space. |
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| 447 | * |
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| 448 | * \param pgm |
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| 449 | * The DMA programm buffer to contain the assembled instruction. |
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| 450 | * |
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| 451 | * \param mod |
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| 452 | * The program instruction modifier for the type of transfer. |
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| 453 | * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and |
---|
| 454 | * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. |
---|
| 455 | * |
---|
| 456 | * \param periph |
---|
| 457 | * The peripheral to notify. |
---|
| 458 | * |
---|
| 459 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 460 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 461 | * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral |
---|
| 462 | * specified. |
---|
| 463 | */ |
---|
| 464 | // Assembler Syntax: DMALDP<S|B> <peripheral> |
---|
| 465 | ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm, |
---|
| 466 | ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); |
---|
| 467 | |
---|
| 468 | /*! |
---|
| 469 | * Assembles a DMALP (Loop) instruction into the microcode program buffer. |
---|
| 470 | * This instruction uses 2 bytes of buffer space. |
---|
| 471 | * |
---|
| 472 | * \param pgm |
---|
| 473 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 474 | * |
---|
| 475 | * \param iterations |
---|
| 476 | * The number of iterations to run for. Valid values are 1 - 256. |
---|
| 477 | * |
---|
| 478 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 479 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 480 | * \retval ALT_E_BAD_ARG Invalid iterations specified. |
---|
| 481 | * \retval ALT_E_BAD_OPERATION All loop registers are in use. |
---|
| 482 | */ |
---|
| 483 | // Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations> |
---|
| 484 | ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm, |
---|
| 485 | uint32_t iterations); |
---|
| 486 | |
---|
| 487 | /*! |
---|
| 488 | * Assembles a DMALPEND (Loop End) instruction into the microcode program |
---|
| 489 | * buffer. This instruction uses 2 bytes of buffer space. |
---|
| 490 | * |
---|
| 491 | * \param pgm |
---|
| 492 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 493 | * |
---|
| 494 | * \param mod |
---|
| 495 | * The program instruction modifier for the loop terminator. Only |
---|
| 496 | * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE |
---|
| 497 | * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. |
---|
| 498 | * |
---|
| 499 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 500 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 501 | * \retval ALT_E_BAD_ARG Invalid instruction modifier specified. |
---|
| 502 | * \retval ALT_E_ARG_RANGE Loop size is too large to be supported. |
---|
| 503 | * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to |
---|
| 504 | * the program buffer before adding this |
---|
| 505 | * DMALPEND instruction. |
---|
| 506 | */ |
---|
| 507 | // Assembler Syntax: DMALPEND[S|B] |
---|
| 508 | ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm, |
---|
| 509 | ALT_DMA_PROGRAM_INST_MOD_t mod); |
---|
| 510 | |
---|
| 511 | /*! |
---|
| 512 | * Assembles a DMALPFE (Loop Forever) instruction into the microcode program |
---|
| 513 | * buffer. No instruction is added to the buffer but a previous DMALPEND to |
---|
| 514 | * create an infinite loop. |
---|
| 515 | * |
---|
| 516 | * \param pgm |
---|
| 517 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 518 | * |
---|
| 519 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 520 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 521 | */ |
---|
| 522 | // Assembler Syntax: DMALPFE |
---|
| 523 | ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm); |
---|
| 524 | |
---|
| 525 | /*! |
---|
| 526 | * Assembles a DMAMOV (Move) instruction into the microcode program buffer. |
---|
| 527 | * This instruction uses 6 bytes of buffer space. |
---|
| 528 | * |
---|
| 529 | * \param pgm |
---|
| 530 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 531 | * |
---|
| 532 | * \param chan_reg |
---|
| 533 | * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR, |
---|
| 534 | * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy |
---|
| 535 | * the value to. |
---|
| 536 | * |
---|
| 537 | * \param val |
---|
| 538 | * The value to write to the specified register. |
---|
| 539 | * |
---|
| 540 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 541 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 542 | * \retval ALT_E_BAD_ARG Invalid channel register specified. |
---|
| 543 | */ |
---|
| 544 | // Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate> |
---|
| 545 | ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm, |
---|
| 546 | ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val); |
---|
| 547 | |
---|
| 548 | /*! |
---|
| 549 | * Assembles a DMANOP (No Operation) instruction into the microcode program |
---|
| 550 | * buffer. This instruction uses 1 byte of buffer space. |
---|
| 551 | * |
---|
| 552 | * \param pgm |
---|
| 553 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 554 | * |
---|
| 555 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 556 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 557 | */ |
---|
| 558 | // Assembler Syntax: DMANOP |
---|
| 559 | ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm); |
---|
| 560 | |
---|
| 561 | /*! |
---|
| 562 | * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode |
---|
| 563 | * program buffer. This instruction uses 1 byte of buffer space. |
---|
| 564 | * |
---|
| 565 | * \param pgm |
---|
| 566 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 567 | * |
---|
| 568 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 569 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 570 | */ |
---|
| 571 | // Assembler Syntax: DMARMB |
---|
| 572 | ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm); |
---|
| 573 | |
---|
| 574 | /*! |
---|
| 575 | * Assembles a DMASEV (Send Event) instruction into the microcode program |
---|
| 576 | * buffer. This instruction uses 2 byte of buffer space. |
---|
| 577 | * |
---|
| 578 | * \param pgm |
---|
| 579 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 580 | * |
---|
| 581 | * \param evt |
---|
| 582 | * The event to send. |
---|
| 583 | * |
---|
| 584 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 585 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 586 | * \retval ALT_E_BAD_ARG Invalid event specified. |
---|
| 587 | */ |
---|
| 588 | // Assembler Syntax: DMASEV <event_num> |
---|
| 589 | ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm, |
---|
| 590 | ALT_DMA_EVENT_t evt); |
---|
| 591 | |
---|
| 592 | /*! |
---|
| 593 | * Assembles a DMAST (Store) instruction into the microcode program buffer. |
---|
| 594 | * This instruction uses 1 byte of buffer space. |
---|
| 595 | * |
---|
| 596 | * \param pgm |
---|
| 597 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 598 | * |
---|
| 599 | * \param mod |
---|
| 600 | * The program instruction modifier for the type of transfer. |
---|
| 601 | * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and |
---|
| 602 | * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. |
---|
| 603 | * |
---|
| 604 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 605 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 606 | */ |
---|
| 607 | // Assembler Syntax: DMAST[S|B] |
---|
| 608 | ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm, |
---|
| 609 | ALT_DMA_PROGRAM_INST_MOD_t mod); |
---|
| 610 | |
---|
| 611 | /*! |
---|
| 612 | * Assembles a DMASTP (Store and notify Peripheral) instruction into the |
---|
| 613 | * microcode program buffer. This instruction uses 2 bytes of buffer space. |
---|
| 614 | * |
---|
| 615 | * \param pgm |
---|
| 616 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 617 | * |
---|
| 618 | * \param mod |
---|
| 619 | * The program instruction modifier for the type of transfer. |
---|
| 620 | * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and |
---|
| 621 | * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options. |
---|
| 622 | * |
---|
| 623 | * \param periph |
---|
| 624 | * The peripheral to notify. |
---|
| 625 | * |
---|
| 626 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 627 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 628 | * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral |
---|
| 629 | * specified. |
---|
| 630 | */ |
---|
| 631 | // Assembler Syntax: DMASTP<S|B> <peripheral> |
---|
| 632 | ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm, |
---|
| 633 | ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph); |
---|
| 634 | |
---|
| 635 | /*! |
---|
| 636 | * Assembles a DMASTZ (Store Zero) instruction into the microcode program |
---|
| 637 | * buffer. This instruction uses 1 byte of buffer space. |
---|
| 638 | * |
---|
| 639 | * \param pgm |
---|
| 640 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 641 | * |
---|
| 642 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 643 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 644 | */ |
---|
| 645 | // Assembler Syntax: DMASTZ |
---|
| 646 | ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm); |
---|
| 647 | |
---|
| 648 | /*! |
---|
| 649 | * Assembles a DMAWFE (Wait For Event) instruction into the microcode program |
---|
| 650 | * buffer. This instruction uses 2 byte of buffer space. |
---|
| 651 | * |
---|
| 652 | * \param pgm |
---|
| 653 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 654 | * |
---|
| 655 | * \param evt |
---|
| 656 | * The event to wait for. |
---|
| 657 | * |
---|
| 658 | * \param invalid |
---|
| 659 | * If invalid is set to true, the instruction will be configured |
---|
| 660 | * to invalidate the instruction cache for the current DMA |
---|
| 661 | * thread. |
---|
| 662 | * |
---|
| 663 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 664 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 665 | * \retval ALT_E_BAD_ARG Invalid event specified. |
---|
| 666 | */ |
---|
| 667 | // Assembler Syntax: DMAWFE <event_num>[, invalid] |
---|
| 668 | ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm, |
---|
| 669 | ALT_DMA_EVENT_t evt, bool invalid); |
---|
| 670 | |
---|
| 671 | /*! |
---|
| 672 | * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode |
---|
| 673 | * program buffer. This instruction uses 2 bytes of buffer space. |
---|
| 674 | * |
---|
| 675 | * \param pgm |
---|
| 676 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 677 | * |
---|
| 678 | * \param periph |
---|
| 679 | * The peripheral to wait on. |
---|
| 680 | * |
---|
| 681 | * \param mod |
---|
| 682 | * The program instruction modifier for the type of transfer. |
---|
| 683 | * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE, |
---|
| 684 | * ALT_DMA_PROGRAM_INST_MOD_BURST, or |
---|
| 685 | * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options. |
---|
| 686 | * |
---|
| 687 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 688 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 689 | * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier |
---|
| 690 | * specified. |
---|
| 691 | */ |
---|
| 692 | // Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph> |
---|
| 693 | ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm, |
---|
| 694 | ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod); |
---|
| 695 | |
---|
| 696 | /*! |
---|
| 697 | * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode |
---|
| 698 | * program buffer. This instruction uses 1 byte of buffer space. |
---|
| 699 | * |
---|
| 700 | * \param pgm |
---|
| 701 | * The DMA programm buffer to contain the assembled instruction. |
---|
| 702 | * |
---|
| 703 | * \retval ALT_E_SUCCESS Successful instruction assembly status. |
---|
| 704 | * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow. |
---|
| 705 | */ |
---|
| 706 | // Assembler Syntax: DMAWMB |
---|
| 707 | ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm); |
---|
| 708 | |
---|
| 709 | /*! |
---|
| 710 | * \addtogroup DMA_CCR Support for DMAMOV CCR |
---|
| 711 | * |
---|
| 712 | * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the |
---|
| 713 | * dynamic microcode programming of the assembler directive: |
---|
| 714 | \verbatim |
---|
| 715 | |
---|
| 716 | DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>] |
---|
| 717 | [SP<imm3>] [SC<imm4>] |
---|
| 718 | [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>] |
---|
| 719 | [DP<imm3>] [DC<imm4>] |
---|
| 720 | [ES<8|16|32|64|128>] |
---|
| 721 | |
---|
| 722 | \endverbatim |
---|
| 723 | * with a DMAMOV instruction (see: alt_dma_program_DMAMOV()). |
---|
| 724 | * |
---|
| 725 | * For example the assembler directive: |
---|
| 726 | \verbatim |
---|
| 727 | DMAMOV CCR SB1 SS32 DB1 DS32 |
---|
| 728 | \endverbatim |
---|
| 729 | * would be dynamically programmed with the following API call: |
---|
| 730 | \verbatim |
---|
| 731 | alt_dma_program_DMAMOV( pgm, |
---|
| 732 | ALT_DMA_PROGRAM_REG_CCR, |
---|
| 733 | ( ALT_DMA_CCR_OPT_SB1 |
---|
| 734 | | ALT_DMA_CCR_OPT_SS32 |
---|
| 735 | | ALT_DMA_CCR_OPT_SA_DEFAULT |
---|
| 736 | | ALT_DMA_CCR_OPT_SP_DEFAULT |
---|
| 737 | | ALT_DMA_CCR_OPT_SC_DEFAULT |
---|
| 738 | | ALT_DMA_CCR_OPT_DB1 |
---|
| 739 | | ALT_DMA_CCR_OPT_DS32 |
---|
| 740 | | ALT_DMA_CCR_OPT_DA_DEFAULT |
---|
| 741 | | ALT_DMA_CCR_OPT_DP_DEFAULT |
---|
| 742 | | ALT_DMA_CCR_OPT_DC_DEFAULT |
---|
| 743 | | ALT_DMA_CCR_OPT_ES8 |
---|
| 744 | ) |
---|
| 745 | ); |
---|
| 746 | \endverbatim |
---|
| 747 | * |
---|
| 748 | * Each CCR option category should be specified regardless of whether it |
---|
| 749 | * specifies a custom value or the normal default value (i.e. an |
---|
| 750 | * ALT_DMA_CCR_OPT_*_DEFAULT. |
---|
| 751 | * |
---|
| 752 | * @{ |
---|
| 753 | */ |
---|
| 754 | |
---|
| 755 | /* |
---|
| 756 | * Source Address {Fixed,Incrementing} |
---|
| 757 | */ |
---|
| 758 | /*! Source Address Fixed address burst. */ |
---|
| 759 | #define ALT_DMA_CCR_OPT_SAF (0 << 0) |
---|
| 760 | /*! Source Address Incrementing address burst. */ |
---|
| 761 | #define ALT_DMA_CCR_OPT_SAI (1 << 0) |
---|
| 762 | /*! Source Address Default value. */ |
---|
| 763 | #define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI |
---|
| 764 | |
---|
| 765 | /* |
---|
| 766 | * Source burst Size (in bits) |
---|
| 767 | */ |
---|
| 768 | /*! Source burst Size of 8 bits. */ |
---|
| 769 | #define ALT_DMA_CCR_OPT_SS8 (0 << 1) |
---|
| 770 | /*! Source burst Size of 16 bits. */ |
---|
| 771 | #define ALT_DMA_CCR_OPT_SS16 (1 << 1) |
---|
| 772 | /*! Source burst Size of 32 bits. */ |
---|
| 773 | #define ALT_DMA_CCR_OPT_SS32 (2 << 1) |
---|
| 774 | /*! Source burst Size of 64 bits. */ |
---|
| 775 | #define ALT_DMA_CCR_OPT_SS64 (3 << 1) |
---|
| 776 | /*! Source burst Size of 128 bits. */ |
---|
| 777 | #define ALT_DMA_CCR_OPT_SS128 (4 << 1) |
---|
| 778 | /*! Source burst Size default bits. */ |
---|
| 779 | #define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8 |
---|
| 780 | |
---|
| 781 | /* |
---|
| 782 | * Source burst Length (in transfer(s)) |
---|
| 783 | */ |
---|
| 784 | /*! Source Burst length of 1 transfer. */ |
---|
| 785 | #define ALT_DMA_CCR_OPT_SB1 (0x0 << 4) |
---|
| 786 | /*! Source Burst length of 2 transfers. */ |
---|
| 787 | #define ALT_DMA_CCR_OPT_SB2 (0x1 << 4) |
---|
| 788 | /*! Source Burst length of 3 transfers. */ |
---|
| 789 | #define ALT_DMA_CCR_OPT_SB3 (0x2 << 4) |
---|
| 790 | /*! Source Burst length of 4 transfers. */ |
---|
| 791 | #define ALT_DMA_CCR_OPT_SB4 (0x3 << 4) |
---|
| 792 | /*! Source Burst length of 5 transfers. */ |
---|
| 793 | #define ALT_DMA_CCR_OPT_SB5 (0x4 << 4) |
---|
| 794 | /*! Source Burst length of 6 transfers. */ |
---|
| 795 | #define ALT_DMA_CCR_OPT_SB6 (0x5 << 4) |
---|
| 796 | /*! Source Burst length of 7 transfers. */ |
---|
| 797 | #define ALT_DMA_CCR_OPT_SB7 (0x6 << 4) |
---|
| 798 | /*! Source Burst length of 8 transfers. */ |
---|
| 799 | #define ALT_DMA_CCR_OPT_SB8 (0x7 << 4) |
---|
| 800 | /*! Source Burst length of 9 transfers. */ |
---|
| 801 | #define ALT_DMA_CCR_OPT_SB9 (0x8 << 4) |
---|
| 802 | /*! Source Burst length of 10 transfers. */ |
---|
| 803 | #define ALT_DMA_CCR_OPT_SB10 (0x9 << 4) |
---|
| 804 | /*! Source Burst length of 11 transfers. */ |
---|
| 805 | #define ALT_DMA_CCR_OPT_SB11 (0xa << 4) |
---|
| 806 | /*! Source Burst length of 12 transfers. */ |
---|
| 807 | #define ALT_DMA_CCR_OPT_SB12 (0xb << 4) |
---|
| 808 | /*! Source Burst length of 13 transfers. */ |
---|
| 809 | #define ALT_DMA_CCR_OPT_SB13 (0xc << 4) |
---|
| 810 | /*! Source Burst length of 14 transfers. */ |
---|
| 811 | #define ALT_DMA_CCR_OPT_SB14 (0xd << 4) |
---|
| 812 | /*! Source Burst length of 15 transfers. */ |
---|
| 813 | #define ALT_DMA_CCR_OPT_SB15 (0xe << 4) |
---|
| 814 | /*! Source Burst length of 16 transfers. */ |
---|
| 815 | #define ALT_DMA_CCR_OPT_SB16 (0xf << 4) |
---|
| 816 | /*! Source Burst length default transfers. */ |
---|
| 817 | #define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1 |
---|
| 818 | |
---|
| 819 | /* |
---|
| 820 | * Source Protection |
---|
| 821 | */ |
---|
| 822 | /*! Source Protection bits for AXI bus ARPROT[2:0]. */ |
---|
| 823 | #define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8) |
---|
| 824 | /*! Source Protection bits default value. */ |
---|
| 825 | #define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0) |
---|
| 826 | |
---|
| 827 | /* |
---|
| 828 | * Source cache |
---|
| 829 | */ |
---|
| 830 | /*! Source Cache bits for AXI bus ARCACHE[2:0]. */ |
---|
| 831 | #define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11) |
---|
| 832 | /*! Source Cache bits default value. */ |
---|
| 833 | #define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0) |
---|
| 834 | |
---|
| 835 | /* |
---|
| 836 | * Destination Address {Fixed,Incrementing} |
---|
| 837 | */ |
---|
| 838 | /*! Destination Address Fixed address burst. */ |
---|
| 839 | #define ALT_DMA_CCR_OPT_DAF (0 << 14) |
---|
| 840 | /*! Destination Address Incrementing address burst. */ |
---|
| 841 | #define ALT_DMA_CCR_OPT_DAI (1 << 14) |
---|
| 842 | /*! Destination Address Default value. */ |
---|
| 843 | #define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI |
---|
| 844 | |
---|
| 845 | /* |
---|
| 846 | * Destination burst Size (in bits) |
---|
| 847 | */ |
---|
| 848 | /*! Destination burst Size of 8 bits. */ |
---|
| 849 | #define ALT_DMA_CCR_OPT_DS8 (0 << 15) |
---|
| 850 | /*! Destination burst Size of 16 bits. */ |
---|
| 851 | #define ALT_DMA_CCR_OPT_DS16 (1 << 15) |
---|
| 852 | /*! Destination burst Size of 32 bits. */ |
---|
| 853 | #define ALT_DMA_CCR_OPT_DS32 (2 << 15) |
---|
| 854 | /*! Destination burst Size of 64 bits. */ |
---|
| 855 | #define ALT_DMA_CCR_OPT_DS64 (3 << 15) |
---|
| 856 | /*! Destination burst Size of 128 bits. */ |
---|
| 857 | #define ALT_DMA_CCR_OPT_DS128 (4 << 15) |
---|
| 858 | /*! Destination burst Size default bits. */ |
---|
| 859 | #define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8 |
---|
| 860 | |
---|
| 861 | /* |
---|
| 862 | * Destination Burst length (in transfer(s)) |
---|
| 863 | */ |
---|
| 864 | /*! Destination Burst length of 1 transfer. */ |
---|
| 865 | #define ALT_DMA_CCR_OPT_DB1 (0x0 << 18) |
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| 866 | /*! Destination Burst length of 2 transfers. */ |
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| 867 | #define ALT_DMA_CCR_OPT_DB2 (0x1 << 18) |
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| 868 | /*! Destination Burst length of 3 transfers. */ |
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| 869 | #define ALT_DMA_CCR_OPT_DB3 (0x2 << 18) |
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| 870 | /*! Destination Burst length of 4 transfers. */ |
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| 871 | #define ALT_DMA_CCR_OPT_DB4 (0x3 << 18) |
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| 872 | /*! Destination Burst length of 5 transfers. */ |
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| 873 | #define ALT_DMA_CCR_OPT_DB5 (0x4 << 18) |
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| 874 | /*! Destination Burst length of 6 transfers. */ |
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| 875 | #define ALT_DMA_CCR_OPT_DB6 (0x5 << 18) |
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| 876 | /*! Destination Burst length of 7 transfers. */ |
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| 877 | #define ALT_DMA_CCR_OPT_DB7 (0x6 << 18) |
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| 878 | /*! Destination Burst length of 8 transfers. */ |
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| 879 | #define ALT_DMA_CCR_OPT_DB8 (0x7 << 18) |
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| 880 | /*! Destination Burst length of 9 transfers. */ |
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| 881 | #define ALT_DMA_CCR_OPT_DB9 (0x8 << 18) |
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| 882 | /*! Destination Burst length of 10 transfers. */ |
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| 883 | #define ALT_DMA_CCR_OPT_DB10 (0x9 << 18) |
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| 884 | /*! Destination Burst length of 11 transfers. */ |
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| 885 | #define ALT_DMA_CCR_OPT_DB11 (0xa << 18) |
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| 886 | /*! Destination Burst length of 12 transfers. */ |
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| 887 | #define ALT_DMA_CCR_OPT_DB12 (0xb << 18) |
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| 888 | /*! Destination Burst length of 13 transfers. */ |
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| 889 | #define ALT_DMA_CCR_OPT_DB13 (0xc << 18) |
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| 890 | /*! Destination Burst length of 14 transfers. */ |
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| 891 | #define ALT_DMA_CCR_OPT_DB14 (0xd << 18) |
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| 892 | /*! Destination Burst length of 15 transfers. */ |
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| 893 | #define ALT_DMA_CCR_OPT_DB15 (0xe << 18) |
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| 894 | /*! Destination Burst length of 16 transfers. */ |
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| 895 | #define ALT_DMA_CCR_OPT_DB16 (0xf << 18) |
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| 896 | /*! Destination Burst length default transfers. */ |
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| 897 | #define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1 |
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| 898 | |
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| 899 | /* |
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| 900 | * Destination Protection |
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| 901 | */ |
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| 902 | /*! Destination Protection bits for AXI bus AWPROT[2:0]. */ |
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| 903 | #define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22) |
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| 904 | /*! Destination Protection bits default value. */ |
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| 905 | #define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0) |
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| 906 | |
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| 907 | /* |
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| 908 | * Destination Cache |
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| 909 | */ |
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| 910 | /*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */ |
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| 911 | #define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25) |
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| 912 | /*! Destination Cache bits default value. */ |
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| 913 | #define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0) |
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| 914 | |
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| 915 | /* |
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| 916 | * Endian Swap size (in bits) |
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| 917 | */ |
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| 918 | /*! Endian Swap: No swap, 8-bit data. */ |
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| 919 | #define ALT_DMA_CCR_OPT_ES8 (0 << 28) |
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| 920 | /*! Endian Swap: Swap bytes within 16-bit data. */ |
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| 921 | #define ALT_DMA_CCR_OPT_ES16 (1 << 28) |
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| 922 | /*! Endian Swap: Swap bytes within 32-bit data. */ |
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| 923 | #define ALT_DMA_CCR_OPT_ES32 (2 << 28) |
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| 924 | /*! Endian Swap: Swap bytes within 64-bit data. */ |
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| 925 | #define ALT_DMA_CCR_OPT_ES64 (3 << 28) |
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| 926 | /*! Endian Swap: Swap bytes within 128-bit data. */ |
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| 927 | #define ALT_DMA_CCR_OPT_ES128 (4 << 28) |
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| 928 | /*! Endian Swap: Default byte swap. */ |
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| 929 | #define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8 |
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| 930 | |
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| 931 | /*! Default CCR register options for a DMAMOV CCR assembler directive. */ |
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| 932 | #define ALT_DMA_CCR_OPT_DEFAULT \ |
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| 933 | (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \ |
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| 934 | ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \ |
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| 935 | ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \ |
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| 936 | ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \ |
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| 937 | ALT_DMA_CCR_OPT_ES8) |
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| 938 | |
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| 939 | /*! |
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| 940 | * @} |
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| 941 | */ |
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| 942 | |
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| 943 | /*! |
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| 944 | * @} |
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| 945 | */ |
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| 946 | |
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| 947 | #ifdef __cplusplus |
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| 948 | } |
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| 949 | #endif /* __cplusplus */ |
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| 950 | |
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| 951 | #endif /* __ALT_DMA_PROGRAM_H__ */ |
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