source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_dma_common.h @ 76386c1

4.115
Last change on this file since 76386c1 was 76386c1, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 26, 2014 at 2:00:44 PM

bsp/altera-cyclone-v: Add DMA support hwlib files

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File size: 7.0 KB
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1/******************************************************************************
2 *
3 * Copyright 2013 Altera Corporation. All Rights Reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
21 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
23 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
27 * OF SUCH DAMAGE.
28 *
29 ******************************************************************************/
30
31#ifndef __ALT_DMA_COMMON_H__
32#define __ALT_DMA_COMMON_H__
33
34#ifdef __cplusplus
35extern "C"
36{
37#endif  /* __cplusplus */
38
39/*!
40 * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
41 *
42 * This module contains the common definitions for the DMA controller related
43 * APIs.
44 *
45 * @{
46 */
47
48/*!
49 * This type definition enumerates the DMA controller channel threads.
50 */
51typedef enum ALT_DMA_CHANNEL_e
52{
53    ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
54    ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
55    ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
56    ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
57    ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
58    ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
59    ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
60    ALT_DMA_CHANNEL_7 = 7  /*!< DMA Channel Thread 7 */
61}
62ALT_DMA_CHANNEL_t;
63
64/*!
65 * This type definition enumerates the SoC system peripherals implementing the
66 * required request interface that enables direct DMA transfers to/from the
67 * device.
68 *
69 * FPGA soft IP interface to the DMA are required to comply with the Synopsys
70 * protocol.
71 *
72 * Request interface numbers 4 through 7 are multiplexed between the CAN
73 * controllers and soft logic implemented in the FPGA fabric. The selection
74 * between the CAN controller and FPGA interfaces is determined at DMA
75 * initialization.
76 */
77typedef enum ALT_DMA_PERIPH_e
78{
79    ALT_DMA_PERIPH_FPGA_0             = 0,  /*!< FPGA soft IP interface 0 */
80    ALT_DMA_PERIPH_FPGA_1             = 1,  /*!< FPGA soft IP interface 1 */
81    ALT_DMA_PERIPH_FPGA_2             = 2,  /*!< FPGA soft IP interface 2 */
82    ALT_DMA_PERIPH_FPGA_3             = 3,  /*!< FPGA soft IP interface 3 */
83
84    ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4,  /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
85    ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5,  /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
86    ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6,  /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
87    ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7,  /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
88
89    ALT_DMA_PERIPH_FPGA_4             = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
90    ALT_DMA_PERIPH_FPGA_5             = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
91    ALT_DMA_PERIPH_FPGA_6             = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
92    ALT_DMA_PERIPH_FPGA_7             = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
93
94    ALT_DMA_PERIPH_CAN0_IF1           = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
95    ALT_DMA_PERIPH_CAN0_IF2           = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
96    ALT_DMA_PERIPH_CAN1_IF1           = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
97    ALT_DMA_PERIPH_CAN1_IF2           = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
98
99    ALT_DMA_PERIPH_I2C0_TX            = 8,  /*!< I<sup>2</sup>C 0 TX */
100    ALT_DMA_PERIPH_I2C0_RX            = 9,  /*!< I<sup>2</sup>C 0 RX */
101    ALT_DMA_PERIPH_I2C1_TX            = 10, /*!< I<sup>2</sup>C 1 TX */
102    ALT_DMA_PERIPH_I2C1_RX            = 11, /*!< I<sup>2</sup>C 1 RX */
103    ALT_DMA_PERIPH_I2C2_TX            = 12, /*!< I<sup>2</sup>C 2 TX */
104    ALT_DMA_PERIPH_I2C2_RX            = 13, /*!< I<sup>2</sup>C 2 RX */
105    ALT_DMA_PERIPH_I2C3_TX            = 14, /*!< I<sup>2</sup>C 3 TX */
106    ALT_DMA_PERIPH_I2C3_RX            = 15, /*!< I<sup>2</sup>C 3 RX */
107    ALT_DMA_PERIPH_SPI0_MASTER_TX     = 16, /*!< SPI 0 Master TX */
108    ALT_DMA_PERIPH_SPI0_MASTER_RX     = 17, /*!< SPI 0 Master RX */
109    ALT_DMA_PERIPH_SPI0_SLAVE_TX      = 18, /*!< SPI 0 Slave TX */
110    ALT_DMA_PERIPH_SPI0_SLAVE_RX      = 19, /*!< SPI 0 Slave RX */
111    ALT_DMA_PERIPH_SPI1_MASTER_TX     = 20, /*!< SPI 1 Master TX */
112    ALT_DMA_PERIPH_SPI1_MASTER_RX     = 21, /*!< SPI 1 Master RX */
113    ALT_DMA_PERIPH_SPI1_SLAVE_TX      = 22, /*!< SPI 1 Slave TX */
114    ALT_DMA_PERIPH_SPI1_SLAVE_RX      = 23, /*!< SPI 1 Slave RX */
115    ALT_DMA_PERIPH_QSPI_FLASH_TX      = 24, /*!< QSPI Flash TX */
116    ALT_DMA_PERIPH_QSPI_FLASH_RX      = 25, /*!< QSPI Flash RX */
117    ALT_DMA_PERIPH_STM                = 26, /*!< System Trace Macrocell */
118    ALT_DMA_PERIPH_RESERVED           = 27, /*!< Reserved */
119    ALT_DMA_PERIPH_UART0_TX           = 28, /*!< UART 0 TX */
120    ALT_DMA_PERIPH_UART0_RX           = 29, /*!< UART 0 RX */
121    ALT_DMA_PERIPH_UART1_TX           = 30, /*!< UART 1 TX */
122    ALT_DMA_PERIPH_UART1_RX           = 31  /*!< UART 1 RX */
123}
124ALT_DMA_PERIPH_t;
125
126/*!
127 * This type enumerates the DMA security state options available.
128 */
129typedef enum ALT_DMA_SECURITY_e
130{
131    ALT_DMA_SECURITY_DEFAULT   = 0, /*!< Use the default security value (e.g. reset default) */
132    ALT_DMA_SECURITY_SECURE    = 1, /*!< Secure */
133    ALT_DMA_SECURITY_NONSECURE = 2  /*!< Non-secure */
134}
135ALT_DMA_SECURITY_t;
136
137/*!
138 * This type definition enumerates the DMA event-interrupt resources.
139 */
140typedef enum ALT_DMA_EVENT_e
141{
142    ALT_DMA_EVENT_0     = 0, /*!< DMA Event 0 */
143    ALT_DMA_EVENT_1     = 1, /*!< DMA Event 1 */
144    ALT_DMA_EVENT_2     = 2, /*!< DMA Event 2 */
145    ALT_DMA_EVENT_3     = 3, /*!< DMA Event 3 */
146    ALT_DMA_EVENT_4     = 4, /*!< DMA Event 4 */
147    ALT_DMA_EVENT_5     = 5, /*!< DMA Event 5 */
148    ALT_DMA_EVENT_6     = 6, /*!< DMA Event 6 */
149    ALT_DMA_EVENT_7     = 7, /*!< DMA Event 7 */
150    ALT_DMA_EVENT_ABORT = 8  /*!< DMA Abort Event */
151}
152ALT_DMA_EVENT_t;
153
154/*!
155 * @}
156 */
157
158#ifdef __cplusplus
159}
160#endif /* __cplusplus */
161
162#endif /* __ALT_DMA_COMMON_H__ */
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