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alt_clock_manager.h @ 9907dde

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Last change on this file since 9907dde was 9907dde, checked in by Sebastian Huber <sebastian.huber@…>, on 08/26/14 at 14:59:56

bsp/altera-cyclone-v: Update to hwlib 13.1

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1	/*! \file
2	* Contains definitions for the Altera Hardware Libraries Clock Manager
3	* Application Programming Interface
4	*/
5
6	/******************************************************************************
7	*
8	* Copyright 2013 Altera Corporation. All Rights Reserved.
9	*
10	* Redistribution and use in source and binary forms, with or without
11	* modification, are permitted provided that the following conditions are met:
12	*
13	* 1. Redistributions of source code must retain the above copyright notice,
14	* this list of conditions and the following disclaimer.
15	*
16	* 2. Redistributions in binary form must reproduce the above copyright notice,
17	* this list of conditions and the following disclaimer in the documentation
18	* and/or other materials provided with the distribution.
19	*
20	* 3. The name of the author may not be used to endorse or promote products
21	* derived from this software without specific prior written permission.
22	*
23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
24	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
26	* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
27	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
28	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
31	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32	* OF SUCH DAMAGE.
33	*
34	******************************************************************************/
35
36	#ifndef __ALT_CLK_MGR_H__
37	#define __ALT_CLK_MGR_H__
38
39	#include "hwlib.h"
40	#include "alt_clock_group.h"
41
42	#ifdef __cplusplus
43	extern "C"
44	{
45	#endif /* __cplusplus */
46
47	/*! \addtogroup CLK_MGR The Clock Manager API
48	*
49	* This module defines the Clock Manager API for accessing, configuring, and
50	* controlling the HPS clock resources.
51	*
52	* @{
53	*/
54
55	/******************************************************************************/
56	/*!
57	* This type definition is an opaque type definition for clock frequency values
58	* in Hz.
59	*/
60	typedef uint32_t alt_freq_t;
61
62	/******************************************************************************/
63	/*!
64	* This type definition enumerates the names of the clock and PLL resources
65	* managed by the Clock Manager.
66	*/
67	typedef enum ALT_CLK_e
68	{
69	/* Clock Input Pins */
70	ALT_CLK_IN_PIN_OSC1,
71	/*!< \b OSC_CLK_1_HPS
72	* External oscillator input:
73	* * Input Pin
74	* * Clock source to Main PLL
75	* * Clock source to SDRAM PLL
76	* and Peripheral PLL if selected via
77	* register write
78	* * Clock source for clock in safe mode
79	*/
80
81	ALT_CLK_IN_PIN_OSC2,
82	/*!< \b OSC_CLK_2_HPS
83	* External Oscillator input:
84	* * Input Pin
85	* * Optional clock source to SDRAM PLL
86	* and Peripheral PLL if selected
87	* * Typically used for Ethernet
88	* reference clock
89	*/
90
91
92	/* FPGA Clock Sources External to HPS */
93	ALT_CLK_F2H_PERIPH_REF,
94	/*<! Alternate clock source from FPGA
95	* for HPS Peripheral PLL. */
96
97	ALT_CLK_F2H_SDRAM_REF,
98	/*<! Alternate clock source from FPGA
99	* for HPS SDRAM PLL. */
100
101
102	/* Other Clock Sources External to HPS */
103	ALT_CLK_IN_PIN_JTAG,
104	/*!< \b JTAG_TCK_HPS
105	* * Input Pin
106	* * External HPS JTAG clock input.
107	*/
108
109	ALT_CLK_IN_PIN_ULPI0,
110	/*!< \b ULPI0_CLK
111	* ULPI Clock provided by external USB0
112	* PHY
113	* * Input Pin
114	*/
115
116	ALT_CLK_IN_PIN_ULPI1,
117	/*!< \b ULPI1_CLK
118	* ULPI Clock provided by external USB1
119	* PHY
120	* * Input Pin
121	*/
122
123	ALT_CLK_IN_PIN_EMAC0_RX,
124	/*!< \b EMAC0:RX_CLK
125	* Rx Reference Clock for EMAC0
126	* * Input Pin
127	*/
128
129	ALT_CLK_IN_PIN_EMAC1_RX,
130	/*!< \b EMAC1:RX_CLK
131	* Rx Reference Clock for EMAC1
132	* * Input Pin
133	*/
134
135
136	/* PLLs */
137	ALT_CLK_MAIN_PLL,
138	/*!< \b main_pll_ref_clkin
139	* Main PLL input reference clock,
140	* used to designate the Main PLL in
141	* PLL clock selections.
142	*/
143
144	ALT_CLK_PERIPHERAL_PLL,
145	/*!< \b periph_pll_ref_clkin
146	* Peripheral PLL input reference
147	* clock, used to designate the
148	* Peripheral PLL in PLL clock
149	* selections.
150	*/
151
152	ALT_CLK_SDRAM_PLL,
153	/*!< \b sdram_pll_ref_clkin
154	* SDRAM PLL input reference clock,
155	* used to designate the SDRAM PLL in
156	* PLL clock selections.
157	*/
158
159	/* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
160	* directly from the osc_clk_1_HPS pin */
161	ALT_CLK_OSC1,
162	/*!< \b osc1_clk
163	* OSC1 Clock Group - The
164	* OSC1 clock group contains
165	* those clocks which are
166	* derived directly from the
167	* osc_clk_1_HPS pin.
168	* * alias for ALT_CLK_IN_PIN_OSC1
169	*/
170
171	/* Main Clock Group - The following clocks are derived from the Main PLL. */
172	ALT_CLK_MAIN_PLL_C0,
173	/!< \b Main PLL C0 Output /
174
175	ALT_CLK_MAIN_PLL_C1,
176	/!< \b Main PLL C1 Output /
177
178	ALT_CLK_MAIN_PLL_C2,
179	/!< \b Main PLL C2 Output /
180
181	ALT_CLK_MAIN_PLL_C3,
182	/!< \b Main PLL C3 Output /
183
184	ALT_CLK_MAIN_PLL_C4,
185	/!< \b Main PLL C4 Output /
186
187	ALT_CLK_MAIN_PLL_C5,
188	/!< \b Main PLL C5 Output /
189
190	ALT_CLK_MPU,
191	/*!< \b mpu_clk
192	* Main PLL C0 Output. Clock for MPU
193	* subsystem, including CPU0 and CPU1.
194	* * Alias for \e ALT_CLK_MAIN_PLL_C0
195	*/
196
197	ALT_CLK_MPU_L2_RAM,
198	/*!< \b mpu_l2_ram_clk
199	* Clock for MPU level 2 (L2) RAM
200	*/
201
202	ALT_CLK_MPU_PERIPH,
203	/*!< \b mpu_periph_clk
204	* Clock for MPU snoop control unit
205	* (SCU) peripherals, such as the
206	* general interrupt controller (GIC)
207	*/
208
209	ALT_CLK_L3_MAIN,
210	/*!< \b main_clk
211	* Main PLL C1 Output
212	* * Alias for \e ALT_CLK_MAIN_PLL_C1
213	*/
214
215	ALT_CLK_L3_MP,
216	/*!< \b l3_mp_clk
217	* Clock for L3 Master Peripheral Switch
218	*/
219
220	ALT_CLK_L3_SP,
221	/*!< \b l3_sp_clk
222	* Clock for L3 Slave Peripheral Switch
223	*/
224
225	ALT_CLK_L4_MAIN,
226	/*!< \b l4_main_clk
227	* Clock for L4 main bus
228	* * Clock for DMA
229	* * Clock for SPI masters
230	*/
231
232	ALT_CLK_L4_MP,
233	/*!< \b l4_mp_clk
234	* Clock for L4 master peripherals (MP) bus
235	*/
236
237	ALT_CLK_L4_SP,
238	/*!< \b l4_sp_clk
239	* Clock for L4 slave peripherals (SP) bus
240	*/
241
242	ALT_CLK_DBG_BASE,
243	/*!< \b dbg_base_clk
244	* Main PLL C2 Output
245	* * Alias for \e ALT_CLK_MAIN_PLL_C2
246	*/
247
248	ALT_CLK_DBG_AT,
249	/*!< \b dbg_at_clk
250	* Clock for CoreSight debug Advanced
251	* Microcontroller Bus Architecture
252	* (AMBA) Trace Bus (ATB)
253	*/
254
255	ALT_CLK_DBG_TRACE,
256	/*!< \b dbg_trace_clk
257	* Clock for CoreSight debug Trace
258	* Port Interface Unit (TPIU)
259	*/
260
261	ALT_CLK_DBG_TIMER,
262	/*!< \b dbg_timer_clk
263	* Clock for the trace timestamp
264	* generator
265	*/
266
267	ALT_CLK_DBG,
268	/*!< \b dbg_clk
269	* Clock for Debug Access Port (DAP)
270	* and debug Advanced Peripheral Bus
271	* (APB)
272	*/
273
274	ALT_CLK_MAIN_QSPI,
275	/*!< \b main_qspi_clk
276	* Main PLL C3 Output. Quad SPI flash
277	* internal logic clock.
278	* * Alias for \e ALT_CLK_MAIN_PLL_C3
279	*/
280
281	ALT_CLK_MAIN_NAND_SDMMC,
282	/*!< \b main_nand_sdmmc_clk
283	* Main PLL C4 Output. Input clock to
284	* flash controller clocks block.
285	* * Alias for \e ALT_CLK_MAIN_PLL_C4
286	*/
287
288	ALT_CLK_CFG,
289	/*!< \b cfg_clk
290	* FPGA manager configuration clock.
291	*/
292
293	ALT_CLK_H2F_USER0,
294	/*!< \b h2f_user0_clock
295	* Clock to FPGA fabric
296	*/
297
298
299	/* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
300	ALT_CLK_PERIPHERAL_PLL_C0,
301	/!< \b Peripheral PLL C0 Output /
302
303	ALT_CLK_PERIPHERAL_PLL_C1,
304	/!< \b Peripheral PLL C1 Output /
305
306	ALT_CLK_PERIPHERAL_PLL_C2,
307	/!< \b Peripheral PLL C2 Output /
308
309	ALT_CLK_PERIPHERAL_PLL_C3,
310	/!< \b Peripheral PLL C3 Output /
311
312	ALT_CLK_PERIPHERAL_PLL_C4,
313	/!< \b Peripheral PLL C4 Output /
314
315	ALT_CLK_PERIPHERAL_PLL_C5,
316	/!< \b Peripheral PLL C5 Output /
317
318	ALT_CLK_USB_MP,
319	/*!< \b usb_mp_clk
320	* Clock for USB
321	*/
322
323	ALT_CLK_SPI_M,
324	/*!< \b spi_m_clk
325	* Clock for L4 SPI master bus
326	*/
327
328	ALT_CLK_QSPI,
329	/*!< \b qspi_clk
330	* Clock for Quad SPI
331	*/
332
333	ALT_CLK_NAND_X,
334	/*!< \b nand_x_clk
335	* NAND flash controller master and
336	* slave clock
337	*/
338
339	ALT_CLK_NAND,
340	/*!< \b nand_clk
341	* Main clock for NAND flash
342	* controller
343	*/
344
345	ALT_CLK_SDMMC,
346	/*!< \b sdmmc_clk
347	* Clock for SD/MMC logic input clock
348	*/
349
350	ALT_CLK_EMAC0,
351	/*!< \b emac0_clk
352	* EMAC 0 clock - Peripheral PLL C0
353	* Output
354	* * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0
355	*/
356
357	ALT_CLK_EMAC1,
358	/*!< \b emac1_clk
359	* EMAC 1 clock - Peripheral PLL C1
360	* Output
361	* * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1
362	*/
363
364	ALT_CLK_CAN0,
365	/*!< \b can0_clk
366	* Controller area network (CAN)
367	* controller 0 clock
368	*/
369
370	ALT_CLK_CAN1,
371	/*!< \b can1_clk
372	* Controller area network (CAN)
373	* controller 1 clock
374	*/
375
376	ALT_CLK_GPIO_DB,
377	/*!< \b gpio_db_clk
378	* Debounce clock for GPIO0, GPIO1,
379	* and GPIO2
380	*/
381
382	ALT_CLK_H2F_USER1,
383	/*!< \b h2f_user1_clock
384	* Clock to FPGA fabric - Peripheral
385	* PLL C5 Output
386	* * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5
387	*/
388
389
390	/* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
391	ALT_CLK_SDRAM_PLL_C0,
392	/!< \b SDRAM PLL C0 Output /
393
394	ALT_CLK_SDRAM_PLL_C1,
395	/!< \b SDRAM PLL C1 Output /
396
397	ALT_CLK_SDRAM_PLL_C2,
398	/!< \b SDRAM PLL C2 Output /
399
400	ALT_CLK_SDRAM_PLL_C3,
401	/!< \b SDRAM PLL C3 Output /
402
403	ALT_CLK_SDRAM_PLL_C4,
404	/!< \b SDRAM PLL C4 Output /
405
406	ALT_CLK_SDRAM_PLL_C5,
407	/!< \b SDRAM PLL C5 Output /
408
409	ALT_CLK_DDR_DQS,
410	/*!< \b ddr_dqs_clk
411	* Clock for MPFE, single-port
412	* controller, CSR access, and PHY -
413	* SDRAM PLL C0 Output
414	* * Alias for \e ALT_CLK_SDRAM_PLL_C0
415	*/
416
417	ALT_CLK_DDR_2X_DQS,
418	/*!< \b ddr_2x_dqs_clk
419	* Clock for PHY - SDRAM PLL C1 Output
420	* * Alias for \e ALT_CLK_SDRAM_PLL_C1
421	*/
422
423	ALT_CLK_DDR_DQ,
424	/*!< \b ddr_dq_clk
425	* Clock for PHY - SDRAM PLL C2 Output
426	* * Alias for \e ALT_CLK_SDRAM_PLL_C2
427	*/
428
429	ALT_CLK_H2F_USER2,
430	/*!< \b h2f_user2_clock
431	* Clock to FPGA fabric - SDRAM PLL C5
432	* Output
433	* * Alias for \e ALT_CLK_SDRAM_PLL_C5
434	*/
435
436	/* Clock Output Pins */
437	ALT_CLK_OUT_PIN_EMAC0_TX,
438	/*!< \b EMAC0:TX_CLK
439	* Tx Reference Clock for EMAC0
440	* * Output Pin
441	*/
442
443	ALT_CLK_OUT_PIN_EMAC1_TX,
444	/*!< \b EMAC1:TX_CLK
445	* Tx Reference Clock for EMAC1
446	* * Output Pin
447	*/
448
449	ALT_CLK_OUT_PIN_SDMMC,
450	/*!< \b SDMMC:CLK
451	* SD/MMC Card Clock
452	* * Output Pin
453	*/
454
455	ALT_CLK_OUT_PIN_I2C0_SCL,
456	/*!< \b I2C0:SCL
457	* I2C Clock for I2C0
458	* * Output Pin
459	*/
460
461	ALT_CLK_OUT_PIN_I2C1_SCL,
462	/*!< \b I2C1:SCL
463	* I2C Clock for I2C1
464	* * Output Pin
465	*/
466
467	ALT_CLK_OUT_PIN_I2C2_SCL,
468	/*!< \b I2C2:SCL
469	* I2C Clock for I2C2/2 wire
470	* * Output Pin
471	*/
472
473	ALT_CLK_OUT_PIN_I2C3_SCL,
474	/*!< \b I2C3:SCL
475	* I2C Clock for I2C1/2 wire
476	* * Output Pin
477	*/
478
479	ALT_CLK_OUT_PIN_SPIM0,
480	/*!< \b SPIM0:CLK
481	* SPI Clock
482	* * Output Pin
483	*/
484
485	ALT_CLK_OUT_PIN_SPIM1,
486	/*!< \b SPIM1:CLK
487	* SPI Clock
488	* * Output Pin
489	*/
490
491	ALT_CLK_OUT_PIN_QSPI,
492	/*!< \b QSPI:CLK
493	* QSPI Flash Clock
494	* * Output Pin
495	*/
496
497	ALT_CLK_UNKNOWN
498	} ALT_CLK_t;
499
500	/******************************************************************************/
501	/*! \addtogroup CLK_MGR_STATUS Clock Manager Status
502	*
503	* This functional group provides status information on various aspects and
504	* properties of the Clock Manager state.
505	*
506	* @{
507	*/
508	/******************************************************************************/
509	/*!
510	* This type definition defines the lock condition status codes for each of the
511	* PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable())
512	* then it contributes to the overall \b clkmgr_IRQ signal assertion state.
513	*/
514	typedef enum ALT_CLK_PLL_LOCK_STATUS_e
515	{
516	ALT_MAIN_PLL_LOCK_ACHV = 0x00000001, /*!< This condition is set if the Main
517	* PLL has achieved lock at least once
518	* since this condition was last
519	* cleared.
520	*/
521	ALT_PERIPH_PLL_LOCK_ACHV = 0x00000002, /*!< This condition is set if the Peripheral
522	* PLL has achieved lock at least once
523	* since this condition was last
524	* cleared.
525	*/
526	ALT_SDR_PLL_LOCK_ACHV = 0x00000004, /*!< This condition is set if the SDRAM
527	* PLL has achieved lock at least once
528	* since this condition was last
529	* cleared.
530	*/
531	ALT_MAIN_PLL_LOCK_LOST = 0x00000008, /*!< This condition is set if the Main
532	* PLL has lost lock at least once
533	* since this condition was last
534	* cleared.
535	*/
536	ALT_PERIPH_PLL_LOCK_LOST = 0x00000010, /*!< This condition is set if the Peripheral
537	* PLL has lost lock at least once
538	* since this condition was last
539	* cleared.
540	*/
541	ALT_SDR_PLL_LOCK_LOST = 0x00000020 /*!< This condition is set if the SDRAM
542	* PLL has lost lock at least once
543	* since this condition was last
544	* cleared.
545	*/
546	} ALT_CLK_PLL_LOCK_STATUS_t;
547
548	/******************************************************************************/
549	/*!
550	* Clear the selected PLL lock status conditions.
551	*
552	* This function clears assertions of one or more of the PLL lock status
553	* conditions.
554	*
555	* NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source
556	* assertion conditions.
557	*
558	* \param lock_stat_mask
559	* Specifies the PLL lock status conditions to clear. \e lock_stat_mask
560	* is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t
561	* values designating the PLL lock conditions to clear.
562	*
563	* \retval ALT_E_SUCCESS Successful status.
564	* \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
565	* unknown condition value.
566	*/
567	ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
568
569	/******************************************************************************/
570	/*!
571	* Returns the PLL lock status condition values.
572	*
573	* This function returns the value of the PLL lock status conditions.
574	*
575	* \returns The current values of the PLL lock status conditions as defined by
576	* the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set
577	* then the condition is asserted.
578	*/
579	uint32_t alt_clk_lock_status_get(void);
580
581	/******************************************************************************/
582	/*!
583	* Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE
584	* otherwise.
585	*
586	* \param pll
587	* The PLL to return the lock status of.
588	*
589	* \retval ALT_E_TRUE The specified PLL is currently locked.
590	* \retval ALT_E_FALSE The specified PLL is currently not locked.
591	* \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock
592	* value.
593	* \internal
594	* NOTE: This function uses the
595	* * \b hps::clkmgr::inter::mainplllocked
596	* * \b hps::clkmgr::inter::perplllocked,
597	* * \b hps::clkmgr::inter::sdrplllocked
598	*
599	* bits to determine if the PLL is locked or not.
600	* \endinternal
601	*/
602	ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
603
604	/! @} /
605
606	/******************************************************************************/
607	/*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options
608	*
609	* When safe mode is enabled, clocks in the HPS are directly generated from the
610	* \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode
611	* request from the reset manager or by a cold reset. Assertion of the safe mode
612	* request from the reset manager sets the safe mode bit in the clock manager
613	* control register. No other control register bits are affected by the safe
614	* mode request from the reset manager.
615	*
616	* While in safe mode, clock manager register settings which control clock
617	* behavior are not changed. However, the output of the registers which control
618	* the clock manager state are forced to the safe mode values such that the
619	* following conditions occur:
620	* * All PLLs are bypassed to the \b osc1_clk clock, including their counters.
621	* * Clock dividers select their default reset values.
622	* * The flash controllers source clock selections are set to the peripheral
623	* PLL.
624	* * All clocks are enabled.
625	* * Safe mode is optionally applied to debug clocks.
626	*
627	* A write by software is the only way to clear the safe mode bit. All registers
628	* and clocks need to be configured correctly and all software-managed clocks
629	* need to be gated off before clearing safe mode. Software can then gate clocks
630	* on as required.
631	*
632	* On cold reset, all clocks are put in safe mode.
633	*
634	* On warm reset, safe mode is optionally and independently applied to debug
635	* clocks and normal (i.e.non-debug) clocks based on clock manager register
636	* settings. The default response for warm reset is to put all clocks in safe
637	* mode.
638	*
639	* The APIs in this group provide control of the Clock Manager safe mode warm
640	* reset response behavior.
641	* @{
642	*/
643
644	/******************************************************************************/
645	/*!
646	* This type definition enumerates the safe mode clock domains under control of
647	* the Clock Manager.
648	*/
649	typedef enum ALT_CLK_SAFE_DOMAIN_e
650	{
651	/*!
652	* This enumeration literal specifies the normal safe mode domain. The
653	* normal domain consists of all clocks except debug clocks.
654	*/
655	ALT_CLK_DOMAIN_NORMAL,
656	/*!
657	* This enumeration literal specifies the debug safe mode domain. The debug
658	* domain consists of all debug clocks.
659	*/
660	ALT_CLK_DOMAIN_DEBUG
661	} ALT_CLK_SAFE_DOMAIN_t;
662
663	/******************************************************************************/
664	/*!
665	* Clear the safe mode status of the Clock Manager following a reset.
666	*
667	* NOTE: Safe mode should only be cleared once clocks have been correctly
668	* configured.
669	*
670	* \retval ALT_E_SUCCESS The operation was succesful.
671	* \retval ALT_E_ERROR The operation failed.
672	*/
673	ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
674
675	/******************************************************************************/
676	/*!
677	* Return whether the specified safe mode clock domain is in safe mode or not.
678	*
679	* \param clk_domain
680	* The safe mode clock domain to check whether in safe mode or not.
681	*
682	* \retval TRUE The safe mode clock domain is in safe mode.
683	* \retval FALSE The safe mode clock domain is not in safe mode.
684	*/
685	bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
686
687	/! @} /
688
689	/******************************************************************************/
690	/*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control
691	*
692	* When a PLL is in bypass, the PLL clock logic is kept in reset. In this
693	* manner, the PLL clock can be free running while it stabilizes and achieves
694	* lock. The bypass logic isolates PLL configuration registers from the clock
695	* while changes are made to the PLL settings.
696	*
697	* The bypass controls are used by software to change the source clock input
698	* reference (for Peripheral and SDRAM PLLs) and is recommended when changing
699	* settings that may affect the ability of the VCO to maintain lock. When a PLL
700	* is taken in or out of bypass the PLL output clocks will pause momentarily
701	* while the clocks are in transition, There will be no glitches or clocks
702	* shorter than the either the old or the new clock period.
703	*
704	* In summary, the PLL bypass controls permit:
705	* * Each PLL to be individually bypassed.
706	* * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs
707	* reference clock input source reference clock selection.
708	* * Isolation of a the PLL VCO frequency registers (multiplier and divider),
709	phase shift registers (negative phase) , and post scale counters.
710	* * Glitch free clock transitions.
711	* @{
712	*/
713	/******************************************************************************/
714	/*!
715	* Disable bypass mode for the specified PLL. This operation takes the PLL out
716	* of bypass mode.
717	*
718	* \param pll
719	* The PLL to take out of bypass mode.
720	*
721	* \retval ALT_E_SUCCESS The operation was succesful.
722	* \retval ALT_E_ERROR The operation failed.
723	* \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock
724	* value.
725	*/
726	ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
727
728	/******************************************************************************/
729	/*!
730	* Enable bypass mode for the specified PLL.
731	*
732	* \param pll
733	* The PLL to put into bypass mode.
734	*
735	* \param use_input_mux
736	* If TRUE then use the PLLs reference clock input source selection
737	* to directly drive the bypass clock. If FALSE then use bypass
738	* clock directly driven by the \b osc1_clk.
739	*
740	* \retval ALT_E_SUCCESS The operation was succesful.
741	* \retval ALT_E_ERROR The operation failed.
742	* \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL
743	* clock value.
744	* \retval ALT_E_INV_OPTION TRUE is an invalid option for
745	* \e use_input_mux with the \e pll selection.
746	*/
747	ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
748	bool use_input_mux);
749
750	/******************************************************************************/
751	/*!
752	* Return whether the specified PLL is in bypass or not.
753	*
754	* \internal
755	* This function must also test the \b clkmgr.ctrl.safemode bit in
756	* addition to the PLLs bypass bit to tell whether the bypass mode is
757	* effect or not.
758	* \endinternal
759	*
760	* \param pll
761	* The PLL to check whether in bypass mode or not.
762	*
763	* \retval ALT_E_TRUE The PLL is in bypass mode.
764	* \retval ALT_E_FALSE The PLL is not in bypass mode.
765	* \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock
766	* value.
767	*/
768	ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
769
770	/! @} /
771
772	/******************************************************************************/
773	/*! \addtogroup CLK_MGR_GATE Clock Gating Control
774	*
775	* This functional group provides gating control of selected clock signals.
776	*
777	* When a clock is enabled, then its clock signal propogates to its respective
778	* clocked IP block(s). When a clock is disabled, then its clock signal is
779	* prevented from propogating to its respective clocked IP block(s).
780	*
781	* The following clocks may be gated:
782	*
783	* * Main PLL Group
784	* - l4_main_clk
785	* - l3_mp_clk
786	* - l4_mp_clk
787	* - l4_sp_clk
788	* - dbg_at_clk
789	* - dbg_clk
790	* - dbg_trace_clk
791	* - dbg_timer_clk
792	* - cfg_clk
793	* - s2f_user0_clk
794	*
795	* * SDRAM PLL Group
796	* - ddr_dqs_clk
797	* - ddr_2x_clk
798	* - ddr_dq_clk
799	* - s2f_user2_clk
800	*
801	* * Peripheral PLL Group
802	* - emac0_clk
803	* - emac1_clk
804	* - usb_mp_clk
805	* - spi_m_clk
806	* - can0_clk
807	* - can1_clk
808	* - gpio_db_clk
809	* - s2f_user1_clk
810	* - sdmmc_clk
811	* - nand_clk
812	* - nand_x_clk
813	* - qspi_clk
814	*
815	* @{
816	*/
817	/******************************************************************************/
818	/*!
819	* Disable the specified clock. Once the clock is disabled, its clock signal does
820	* not propogate to its clocked elements.
821	*
822	* \param clk
823	* The clock to disable.
824	*
825	* \retval ALT_E_SUCCESS The operation was succesful.
826	* \retval ALT_E_ERROR The operation failed.
827	* \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
828	* value.
829	*/
830	ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
831
832	/******************************************************************************/
833	/*!
834	* Enable the specified clock. Once the clock is enabled, its clock signal
835	* propogates to its elements.
836	*
837	* \param clk
838	* The clock to enable.
839	*
840	* \retval ALT_E_SUCCESS The operation was succesful.
841	* \retval ALT_E_ERROR The operation failed.
842	* \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
843	* value.
844	*/
845	ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
846
847	/******************************************************************************/
848	/*!
849	* Return whether the specified clock is enabled or not.
850	*
851	* \param clk
852	* The clock to check whether enabled or not.
853	*
854	* \retval ALT_E_TRUE The clock is enabled.
855	* \retval ALT_E_FALSE The clock is not enabled.
856	* \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
857	* value.
858	*/
859	ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
860
861	/! @} /
862
863	/******************************************************************************/
864	/*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection
865	*
866	* This API group provide access and control to the input reference clock source
867	* selection for a clock or PLL.
868	*
869	* \internal
870	* These are the clocks that have software configurable input reference clock
871	* source selection available. Each clock below is listed with its valid
872	* input reference clock source selections.
873	*
874	* + Valid reference clock input selections for \b sdram_pll_ref_clkin
875	* - osc_clk_1
876	* - osc_clk_2
877	* - f2h_sdram_ref_clk
878	*
879	* + Valid reference clock input selections for \b periph_pll_ref_clkin
880	* - osc_clk_1
881	* - osc_clk_2,
882	* - f2h_periph_ref_clk
883	*
884	* + Valid reference clock input selections for \b l4_mp_clk
885	* - periph_base_clk
886	* - main_clk
887	*
888	* + Valid reference clock input selections for \b l4_sp_clk
889	* - periph_base_clk
890	* - main_clk
891	*
892	* + Valid reference clock input selections for \b sdmmc_clk
893	* - f2h_periph_ref_clk
894	* - main_nand_sdmmc_clk
895	* - periph_nand_sdmmc_clk
896	*
897	* + Valid reference clock input selections for \b nand_clk
898	* - f2h_periph_ref_clk
899	* - main_nand_sdmmc_clk
900	* - periph_nand_sdmmc_clk
901	*
902	* + Valid reference clock input selections for \b qspi_clk
903	* - f2h_periph_ref_clk
904	* - main_qspi_clk
905	* - periph_qspi_clk
906	*
907	* \endinternal
908	* @{
909	*/
910	/******************************************************************************/
911	/*!
912	* Get the input reference clock source selection value for the specified clock
913	* or PLL.
914	*
915	* NOTE: This function returns a clock value even though \e clk may specify a
916	* clock that does not have a selectable input reference clock source. In
917	* this case, the clock value returned is the static clock source for the
918	* specified clock. For example calling alt_clk_source_get() with \e clk
919	* set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1.
920	*
921	* \param clk
922	* The clock or PLL to retrieve the input reference clock source
923	* selection value for.
924	*
925	* \returns The clock's currently selected input reference clock source.
926	*/
927	ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
928
929	/******************************************************************************/
930	/*!
931	* Set the specified clock's input reference clock source selection.
932	*
933	* \param clk
934	* The clock or PLL to set the input reference clock source
935	* selection for.
936	*
937	* \param ref_clk
938	* The input reference clock source selection value.
939	*
940	* \retval ALT_E_SUCCESS The operation was succesful.
941	* \retval ALT_E_ERROR The operation failed.
942	* \retval ALT_E_BAD_ARG The \e clk argument designates a clock that
943	* does not have a selectable input reference
944	* clock source.
945	* \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that
946	* is an invalid reference clock source for the
947	* specified clock.
948	*/
949	ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
950	ALT_CLK_t ref_clk);
951
952	/! @} /
953
954	/******************************************************************************/
955	/*! \addtogroup CLK_MGR_FREQ Clock Frequency Control
956	*
957	* This API group provides access and control of the output frequency of a clock
958	* or PLL.
959	*
960	* @{
961	*/
962
963	/******************************************************************************/
964	/*!
965	* Set the external clock frequency value.
966	*
967	* The function is used to specify the frequency of the external clock source as
968	* a measure of Hz. The supplied frequency should be within the Fmin and Fmax
969	* values allowed for the external clock source.
970	*
971	* \param clk
972	* The external clock source. Valid external clocks are
973	* * \e ALT_CLK_OSC1
974	* * \e ALT_CLK_OSC2
975	* * \e ALT_CLK_F2H_PERIPH_REF
976	* * \e ALT_CLK_F2H_SDRAM_REF
977	*
978	* \param freq
979	* The frequency of the external clock in Hz.
980	*
981	* \retval ALT_E_SUCCESS The operation was succesful.
982	* \retval ALT_E_ERROR The operation failed.
983	* \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk
984	* argument is bad or not a valid external clock
985	* source
986	* \retval ALT_E_ARG_RANGE The frequency value violates the range constraints
987	* for the specified clock.
988
989	*/
990	ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
991	alt_freq_t freq);
992
993	/******************************************************************************/
994	/*!
995	* Get the external clock frequency value.
996	*
997	* This function returns the frequency of the external clock source as
998	* a measure of Hz.
999	*
1000	* \param clk
1001	* The external clock source. Valid external clocks are
1002	* * \e ALT_CLK_OSC1
1003	* * \e ALT_CLK_OSC2
1004	* * \e ALT_CLK_F2H_PERIPH_REF
1005	* * \e ALT_CLK_F2H_SDRAM_REF
1006	*
1007	* \retval freq
1008	* The frequency of the external clock in Hz.
1009	*
1010	*/
1011	alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
1012
1013	/******************************************************************************/
1014	/*!
1015	* This type definition defines a structure to contain the generalized
1016	* configuration settings for a PLL.
1017	*/
1018	typedef struct ALT_CLK_PLL_CFG_s
1019	{
1020	ALT_CLK_t ref_clk; /!< PLL Reference Clock Source /
1021	uint32_t mult; /*!< VCO Frequency Configuration -
1022	* Multiplier (M) value, range 1 to 4096
1023	*/
1024	uint32_t div; /*!< VCO Frequency Configuration -
1025	* Divider (N) value, range 1 to 64
1026	*/
1027	uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) -
1028	* range 1 to 512
1029	*/
1030	uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of
1031	* negative phase shift per increment,
1032	* range 0 to 4096
1033	*/
1034	} ALT_CLK_PLL_CFG_t;
1035
1036	/******************************************************************************/
1037	/*!
1038	* Get the current PLL configuration.
1039	*
1040	* \param pll
1041	* The PLL to get the configuration from.
1042	*
1043	* \param pll_cfg
1044	* [out] Pointer to an output parameter variable for the returned
1045	* PLL configuration.
1046	*
1047	* \retval ALT_E_SUCCESS The operation was succesful.
1048	* \retval ALT_E_ERROR The operation failed.
1049	*/
1050	ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
1051	ALT_CLK_PLL_CFG_t* pll_cfg);
1052
1053	/******************************************************************************/
1054	/*!
1055	* Set the PLL configuration using the configuration parameters specified in
1056	* \e pll_cfg.
1057	*
1058	* \param pll
1059	* The PLL to set the configuration for.
1060	*
1061	* \param pll_cfg
1062	* Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired
1063	* PLL configuration.
1064	*
1065	* \retval ALT_E_SUCCESS The operation was succesful.
1066	* \retval ALT_E_ERROR The operation failed.
1067	*/
1068	ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
1069	const ALT_CLK_PLL_CFG_t* pll_cfg);
1070
1071	/******************************************************************************/
1072	/*!
1073	* Get the current PLL VCO frequency configuration.
1074	*
1075	* \param pll
1076	* The PLL to get the VCO frequency configuration for.
1077	*
1078	* \param mult
1079	* [out] Pointer to an output variable for the returned
1080	* configured PLL VCO multiplier (M) value.
1081	*
1082	* \param div
1083	* [out] Pointer to an output variable for the returned
1084	* configured PLL VCO divider (N) value.
1085	*
1086	* \retval ALT_E_SUCCESS The operation was succesful.
1087	* \retval ALT_E_ERROR The operation failed.
1088	*/
1089	ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
1090	uint32_t* mult,
1091	uint32_t* div);
1092
1093	/******************************************************************************/
1094	/*!
1095	* Set the PLL VCO frequency configuration using the supplied multiplier and
1096	* divider arguments.
1097	*
1098	* \param pll
1099	* The PLL to set the VCO frequency configuration for.
1100	*
1101	* \param mult
1102	* The PLL VCO multiplier (M). Expected argument range 1 to 4096.
1103	*
1104	* \param div
1105	* The PLL VCO divider (N). Expected argument range 1 to 64.
1106	*
1107	* \retval ALT_E_SUCCESS The operation was succesful.
1108	* \retval ALT_E_ERROR The operation failed.
1109	*/
1110	ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
1111	uint32_t mult,
1112	uint32_t div);
1113
1114	/******************************************************************************/
1115	/*!
1116	* Get the VCO frequency of the specified PLL.
1117	*
1118	* \param pll
1119	* The PLL to retrieve the VCO frequency from.
1120	*
1121	* \param freq
1122	* [out] Pointer to the an output parameter variable to return the
1123	* PLL VCO frequency value. The frequency value is returned as a
1124	* measures of Hz.
1125	*
1126	* \retval ALT_E_SUCCESS The operation was succesful.
1127	* \retval ALT_E_ERROR The operation failed.
1128	* \retval ALT_E_BAD_ARG A bad argument value was passed. Either
1129	* the \e pll argument is invalid or a bad
1130	* \e freq pointer value was passed.
1131	*/
1132	ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
1133	alt_freq_t* freq);
1134
1135	/******************************************************************************/
1136	/*!
1137	* Get the PLL frequency guard band value.
1138	*
1139	* \param pll
1140	* The PLL from which to return the current guard band value.
1141	*
1142	* \returns The current guard band range in effect for the PLL.
1143	*/
1144	uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
1145
1146	/******************************************************************************/
1147	/*!
1148	* Set the PLL frequency guard band value.
1149	*
1150	* Once a PLL has achieved lock, any changes to the PLL VCO frequency that are
1151	* within a specific guard band range (default value 20%) of the reference
1152	* period should not cause the PLL to lose lock.
1153	*
1154	* Programmatic changes to the PLL frequency within this guard band range are
1155	* permitted to be made without the risk of breaking lock during the transition
1156	* to the new frequency.
1157	*
1158	* The clk_mgr_pll_guard_band_set() function changes the guard band from its
1159	* current value to permit a more lenient or stringent policy to be in effect in
1160	* the implementation of the functions configuring PLL VCO frequency. The
1161	* rationale for changing the default guard band value might be to accommodate
1162	* unexpected environmental conditions (noise, temperature, and other
1163	* instability factors) that may affect the PLLs ability to maintain lock during
1164	* a frequency change.
1165	*
1166	* \param pll
1167	* The PLL to set the guard band value for.
1168	*
1169	* \param guard_band
1170	* The guard band value. Value should be 0 <= \e guard_band <= 100.
1171	*
1172	* \retval ALT_E_SUCCESS The operation was succesful.
1173	* \retval ALT_E_ERROR The operation failed.
1174	* \retval ALT_E_ARG_RANGE The guard band value violates its range constraint.
1175	*/
1176	ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
1177	uint32_t guard_band);
1178
1179	/******************************************************************************/
1180	/*!
1181	* Get the configured divider value for the specified clock.
1182	*
1183	* This function is used to get the configured values of both internal and
1184	* external clock dividers. The internal divider (PLL counters C0-C5) values
1185	* are retrieved by specifying the clock name that is the divider output
1186	* (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n
1187	* It returns the actual divider value, not the encoded bitfield stored
1188	* in the register, due to the variety of different encodings.
1189	*
1190	* \param clk
1191	* The clock divider to get the value from.
1192	*
1193	* \param div
1194	* [out] Pointer to an output variable for the returned clock
1195	* divider value.
1196	*
1197	* \retval ALT_E_SUCCESS The operation was succesful.
1198	* \retval ALT_E_ERROR The operation failed.
1199	* \retval ALT_E_BAD_ARG An invalid clock argument was specified or a
1200	* clock that does not have a divider.
1201	*/
1202	ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
1203	uint32_t* div);
1204
1205	/******************************************************************************/
1206	/*!
1207	* Set the divider value for the specified clock.
1208	*
1209	* This function is used to set the values of both internal and external clock
1210	* dividers. The internal divider (PLL counters C0-C5) values are set by
1211	* specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is
1212	* used to set the Main PLL C0 counter value).
1213	*
1214	* \param clk
1215	* The clock divider to set the value for.
1216	*
1217	* \param div
1218	* The clock divider value. NOTE: The valid range of clock divider
1219	* values depends on the clock being configured. This is the
1220	* real divisor ratio, not how the divisor is coded into the
1221	* register, and is always one or greater.
1222	*
1223	* \retval ALT_E_SUCCESS The operation was succesful.
1224	* \retval ALT_E_ERROR The operation failed.
1225	* \retval ALT_E_BAD_ARG An invalid clock argument was specified or a
1226	* clock that does not have a divider.
1227	* \retval ALT_E_ARG_RANGE The divider value violates the range constraints
1228	* for the clock divider.
1229	*/
1230	ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
1231	uint32_t div);
1232
1233	/******************************************************************************/
1234	/*!
1235	* Get the output frequency of the specified clock.
1236	*
1237	* \param clk
1238	* The clock to retrieve the output frequency from.
1239	*
1240	* \param freq
1241	* [out] Pointer to the an output parameter variable to return the
1242	* clock output frequency value. The frequency value is returned as
1243	* a measures of Hz.
1244	*
1245	* \retval ALT_E_SUCCESS The operation was succesful.
1246	* \retval ALT_E_ERROR The operation failed.
1247	* \retval ALT_E_BAD_ARG A bad argument value was passed. Either
1248	* the \e clk argument is invalid or a bad
1249	* \e freq pointer value was passed.
1250	*/
1251	ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
1252	alt_freq_t* freq);
1253
1254	/! @} /
1255
1256	/******************************************************************************/
1257	/*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management
1258	*
1259	* The functions in this group provide management of interrupts originating from
1260	* the Clock Manager.
1261	*
1262	* The following interrupt request (IRQ) signals are sourced from the Clock
1263	* Manager:
1264	*
1265	* * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock
1266	* status interrupt is the logical \e OR of six interrupt
1267	* sources defining the loss or achievement of lock status for
1268	* each PLL. The six PLL lock status conditions are:
1269	* - Main PLL Achieved Lock
1270	* - Main PLL Lost Lock
1271	* - Peripheral PLL Achieved Lock
1272	* - Peripheral PLL Lost Lock
1273	* - SDRAM PLL Achieved Lock
1274	* - SDRAM PLL Lost Lock
1275	*
1276	* They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t.
1277	*
1278	* Each PLL lock condition may be individually disabled/enabled
1279	* as a contributor to the determination of the \b clkmgr_IRQ
1280	* assertion status.
1281	*
1282	* The alt_clk_lock_status_clear() function is used to clear
1283	* the PLL lock conditions causing the \b clkmgr_IRQ
1284	* assertion.
1285	*
1286	* * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the
1287	* MPU to "wake up" after a transition of the Main PLL into
1288	* or out of bypass mode has been safely achieved. The need
1289	* for the "wake up" notification is because the PLL clocks
1290	* pause for a short number of clock cycles during bypass
1291	* state transition. ARM recommeds that the CPUs are placed
1292	* in standby if the clocks are ever paused.
1293	*
1294	* NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not
1295	* be part of the public API although clearly it has important utility in
1296	* implementing safe changes to PLL settings and transitions into and out
1297	* of bypass mode.
1298	* @{
1299	*/
1300
1301	/******************************************************************************/
1302	/*!
1303	* Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
1304	*
1305	* This function disables one or more of the lock status conditions as
1306	* contributors to the \b clkmgr_IRQ interrupt signal state.
1307	*
1308	* NOTE: A set bit for a PLL lock status condition in the mask value does not
1309	* have the effect of enabling it as a contributor to the \b clkmgr_IRQ
1310	* interrupt signal state. The function alt_clk_irq_enable is used to enable PLL
1311	* lock status source condition(s).
1312	*
1313	* \param lock_stat_mask
1314	* Specifies the PLL lock status conditions to disable as interrupt
1315	* source contributors. \e lock_stat_mask is a mask of logically
1316	* OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
1317	* conditions to disable.
1318	*
1319	* \retval ALT_E_SUCCESS Successful status.
1320	* \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
1321	* unknown condition value.
1322	*/
1323	ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1324
1325	/******************************************************************************/
1326	/*!
1327	* Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
1328	*
1329	* This function enables one or more of the lock status conditions as
1330	* contributors to the \b clkmgr_IRQ interrupt signal state.
1331	*
1332	* NOTE: A cleared bit for any PLL lock status condition in the mask value does
1333	* not have the effect of disabling it as a contributor to the \b clkmgr_IRQ
1334	* interrupt signal state. The function alt_clk_irq_disable is used to disable
1335	* PLL lock status source condition(s).
1336	*
1337	* \param lock_stat_mask
1338	* Specifies the PLL lock status conditions to enable as interrupt
1339	* source contributors. \e lock_stat_mask is a mask of logically
1340	* OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
1341	* conditions to enable.
1342	*
1343	* \retval ALT_E_SUCCESS Successful status.
1344	* \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
1345	* unknown condition value.
1346	*/
1347	ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1348
1349	/! @} /
1350
1351	/******************************************************************************/
1352	/*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration
1353	*
1354	* This API provides the ability to safely set the configuration of a clock
1355	* group with a single function call.
1356	*
1357	* A clock group is defined as set of clocks and signals generated from a common
1358	* PLL VCO. The PLL and its derived clocks are treated as a single clock
1359	* group. The clocks sourced directly or indirectly from the PLL may or may not
1360	* have these features:
1361	* * Clock Gates
1362	* * Clock Dividers
1363	* * Clock Source Selection Options
1364	*
1365	* The use case for application of the Clock Group Configuration functions is the
1366	* ability to safely configure an entire clock group from a known good clock
1367	* group configuration using the run-time function alt_clk_group_cfg_raw_set().
1368	*
1369	* A known good clock group configuration may be generated by one of the
1370	* following methods:
1371	*
1372	* * As static design information generated by an ACDS clock configuration tool
1373	* and passed to embedded software for dynamic loading.
1374	*
1375	* * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has
1376	* programmatically established a known good clock group configuration using
1377	* the clock manager API configuration functions.
1378	*
1379	* @{
1380	*/
1381
1382	/******************************************************************************/
1383	/*!
1384	* Get the raw configuration state of the designated clock group.
1385	*
1386	* This function is used to capture the configuration state of the specified
1387	* clock group in a private (raw) data structure. The raw data structure may be
1388	* saved and used later to restore the clock group configuration using
1389	* alt_clk_group_cfg_raw_get().
1390	*
1391	* \param clk_group
1392	* The clock group configuration to capture.
1393	*
1394	* \param clk_group_raw_cfg
1395	* [out] A pointer to a private (raw) data structure to store the
1396	* captured clock group configuration.
1397	*
1398	* \retval ALT_E_SUCCESS Successful status.
1399	* \retval ALT_E_ERROR Details about error status code
1400	*/
1401	ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
1402	ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1403
1404	/******************************************************************************/
1405	/*!
1406	* Set the clock group configuration.
1407	*
1408	* This function is used to safely set the configuration state of a clock
1409	* group from a raw clock group configuration specification. The raw clock
1410	* group configuration specification may be a configuration previously
1411	* captured with alt_clk_group_cfg_raw_get() or a group clock configuration
1412	* generated by an external utility.
1413	*
1414	* \param clk_group_raw_cfg
1415	* A pointer to the specification to use in the configuration of
1416	* the clock group.
1417	*
1418	* \retval ALT_E_SUCCESS Successful status.
1419	* \retval ALT_E_ERROR Details about error status code
1420	* \retval ALT_E_BAD_VERSION The clock group configuration specification is
1421	* invalid for this device.
1422	*/
1423	ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1424
1425	ALT_STATUS_CODE alt_clk_clkmgr_init(void);
1426
1427	/! @} /
1428
1429	/! @} /
1430	#ifdef __cplusplus
1431	}
1432
1433	#endif /* __cplusplus */
1434	#endif /* __ALT_CLK_MGR_H__ */

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source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/alt_clock_manager.h @ 9907dde

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