1 | /*! \file |
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2 | * Contains the definition of an opaque data structure that contains raw |
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3 | * configuration information for a clock group. |
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4 | */ |
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5 | |
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6 | /****************************************************************************** |
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7 | * |
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8 | * Copyright 2013 Altera Corporation. All Rights Reserved. |
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9 | * |
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10 | * Redistribution and use in source and binary forms, with or without |
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11 | * modification, are permitted provided that the following conditions are met: |
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12 | * |
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13 | * 1. Redistributions of source code must retain the above copyright notice, |
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14 | * this list of conditions and the following disclaimer. |
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15 | * |
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16 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
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17 | * this list of conditions and the following disclaimer in the documentation |
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18 | * and/or other materials provided with the distribution. |
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19 | * |
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20 | * 3. The name of the author may not be used to endorse or promote products |
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21 | * derived from this software without specific prior written permission. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR |
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24 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO |
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26 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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27 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT |
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28 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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31 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY |
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32 | * OF SUCH DAMAGE. |
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33 | * |
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34 | ******************************************************************************/ |
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35 | |
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36 | #ifndef __ALT_CLK_GRP_H__ |
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37 | #define __ALT_CLK_GRP_H__ |
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38 | |
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39 | #include "hwlib.h" |
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40 | #include "socal/alt_clkmgr.h" |
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41 | |
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42 | #ifdef __cplusplus |
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43 | extern "C" |
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44 | { |
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45 | #endif /* __cplusplus */ |
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46 | |
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47 | |
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48 | /*! This type definition enumerates the clock groups |
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49 | */ |
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50 | typedef enum ALT_CLK_GRP_e |
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51 | { |
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52 | ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ |
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53 | |
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54 | ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ |
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55 | |
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56 | ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ |
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57 | |
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58 | } ALT_CLK_GRP_t; |
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59 | |
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60 | |
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61 | |
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62 | /*! This type definition defines an opaque data structure for holding the |
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63 | * configuration settings for a complete clock group. |
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64 | */ |
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65 | typedef struct ALT_CLK_GROUP_RAW_CFG_s |
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66 | { |
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67 | uint32_t verid; /*!< SoC FPGA version identifier. This field |
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68 | * encapsulates the silicon identifier and |
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69 | * version information associated with this |
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70 | * clock group configuration. It is used to |
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71 | * assert that this clock group configuration |
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72 | * is valid for this device. |
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73 | */ |
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74 | uint32_t siliid2; /*!< Reserved register - reserved for future |
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75 | * device IDs or capability flags/ |
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76 | */ |
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77 | ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator */ |
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78 | |
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79 | |
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80 | /*! This union holds the raw register values for configuration of the set of |
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81 | * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator |
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82 | * identifies the valid clock group union data member. |
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83 | */ |
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84 | union ALT_CLK_GROUP_RAW_CFG_u |
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85 | { |
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86 | ALT_CLKMGR_MAINPLL_t mainpllgrp; /*!< Raw clock group configuration for Main PLL group */ |
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87 | ALT_CLKMGR_PERPLL_t perpllgrp; /*!< Raw clock group configuration for Peripheral PLL group */ |
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88 | ALT_CLKMGR_SDRPLL_t sdrpllgrp; /*!< Raw clock group configuration for SDRAM PLL group */ |
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89 | } clkgrp; |
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90 | } ALT_CLK_GROUP_RAW_CFG_t; |
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91 | |
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92 | #ifdef __cplusplus |
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93 | } |
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94 | #endif /* __cplusplus */ |
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95 | #endif /* __ALT_CLK_GRP_H__ */ |
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