source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @ af80b0a

5
Last change on this file since af80b0a was af80b0a, checked in by Sebastian Huber <sebastian.huber@…>, on 02/18/19 at 07:24:37

bsp/altera-cyclone-v: Use FDT for clock frequency

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File size: 3.0 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Altera Cyclone-V platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10RTEMS_TOP(../../../../../..)
11RTEMS_SOURCE_TOP
12RTEMS_BUILD_TOP
13RTEMS_BSP_LINKCMDS
14
15RTEMS_CANONICAL_TARGET_CPU
16AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
17RTEMS_BSP_CONFIGURE
18
19
20
21RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
22RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
23
24RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
25RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
26
27RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
28RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
29
30RTEMS_BSPOPTS_SET([BSP_FDT_IS_SUPPORTED],[*],[1])
31RTEMS_BSPOPTS_HELP([BSP_FDT_IS_SUPPORTED],[define if FDT is supported])
32
33RTEMS_BSPOPTS_SET([BSP_START_COPY_FDT_FROM_U_BOOT],[*],[1])
34RTEMS_BSPOPTS_HELP([BSP_START_COPY_FDT_FROM_U_BOOT],[copy the U-Boot provided FDT to an internal storage])
35
36RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_SIZE_MAX],[*],[262144])
37RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_SIZE_MAX],[maximum size of the FDT blob in bytes])
38
39RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_READ_ONLY],[*],[1])
40RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_READ_ONLY],[place the FDT blob into the read-only data area])
41
42RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[*],[1])
43RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[copy the FDT blob into the read-only load area via bsp_fdt_copy()])
44
45RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[])
46RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[define to set ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz, otherwise alt_clk_freq_get() is used])
47
48RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[1])
49RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
50[This sets a mode where the time runs as fast as possible when a clock ISR
51occurs while the IDLE thread is executing.  This can significantly reduce
52simulation times.])
53
54RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[0])
55RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
56
57RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_CONSOLE],[*],[0])
58RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_CONSOLE],[configuration for console (UART 0)])
59
60RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_UART_1],[*],[0])
61RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1])
62
63RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U])
64RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs])
65
66RTEMS_BSPOPTS_SET([BSP_USE_UART_INTERRUPTS],[*],[1])
67RTEMS_BSPOPTS_HELP([BSP_USE_UART_INTERRUPTS],[enable usage of interrupts for the UART modules])
68
69RTEMS_BSPOPTS_SET([CYCLONE_V_NO_I2C],[*],[1])
70RTEMS_BSPOPTS_HELP([CYCLONE_V_NO_I2C],
71[Number of configured I2C buses. Note that each bus has to be configured in an
72apropriate i2cdrv_config array.])
73
74RTEMS_BSPOPTS_SET([CYCLONE_V_I2C0_SPEED],[*],[100000])
75RTEMS_BSPOPTS_HELP([CYCLONE_V_I2C0_SPEED],[speed for I2C0 in HZ])
76
77
78RTEMS_BSP_CLEANUP_OPTIONS
79
80AC_CONFIG_FILES([Makefile])
81AC_OUTPUT
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