source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @ 37dc047

5
Last change on this file since 37dc047 was 37dc047, checked in by Sebastian Huber <sebastian.huber@…>, on 04/21/18 at 08:00:43

bsps: Remove AC_CONFIG_SRCDIR()

This AC_CONFIG_SRCDIR() is just a sanity check in this insane build
system. Since all content of
c/src/lib/libbsp/@RTEMS_CPU@/@RTEMS_BSP_FAMILY@ is bound to be moved it
makes no sense to keep it.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Altera Cyclone-V platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10RTEMS_TOP(../../../../../..)
11RTEMS_SOURCE_TOP
12RTEMS_BUILD_TOP
13RTEMS_BSP_LINKCMDS
14
15RTEMS_CANONICAL_TARGET_CPU
16AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
17RTEMS_BSP_CONFIGURE
18
19
20
21RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
22RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
23
24RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
25RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
26
27RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
28RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
29
30RTEMS_BSPOPTS_SET([BSP_START_COPY_FDT_FROM_U_BOOT],[*],[1])
31RTEMS_BSPOPTS_HELP([BSP_START_COPY_FDT_FROM_U_BOOT],[copy the U-Boot provided FDT to an internal storage])
32
33RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_SIZE_MAX],[*],[262144])
34RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_SIZE_MAX],[maximum size of the FDT blob in bytes])
35
36RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_READ_ONLY],[*],[1])
37RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_READ_ONLY],[place the FDT blob into the read-only data area])
38
39RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[*],[1])
40RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[copy the FDT blob into the read-only load area via bsp_fdt_copy()])
41
42RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U])
43RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
44RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
45
46RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[1])
47RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
48[This sets a mode where the time runs as fast as possible when a clock ISR
49occurs while the IDLE thread is executing.  This can significantly reduce
50simulation times.])
51
52RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[0])
53RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
54
55RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_CONSOLE],[*],[0])
56RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_CONSOLE],[configuration for console (UART 0)])
57
58RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_UART_1],[*],[0])
59RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1])
60
61RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U])
62RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs])
63
64RTEMS_BSPOPTS_SET([BSP_USE_UART_INTERRUPTS],[*],[1])
65RTEMS_BSPOPTS_HELP([BSP_USE_UART_INTERRUPTS],[enable usage of interrupts for the UART modules])
66
67RTEMS_BSPOPTS_SET([CYCLONE_V_NO_I2C],[*],[1])
68RTEMS_BSPOPTS_HELP([CYCLONE_V_NO_I2C],
69[Number of configured I2C buses. Note that each bus has to be configured in an
70apropriate i2cdrv_config array.])
71
72RTEMS_BSPOPTS_SET([CYCLONE_V_I2C0_SPEED],[*],[100000])
73RTEMS_BSPOPTS_HELP([CYCLONE_V_I2C0_SPEED],[speed for I2C0 in HZ])
74
75
76RTEMS_BSP_CLEANUP_OPTIONS
77
78AC_CONFIG_FILES([Makefile])
79AC_OUTPUT
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