source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 3.2 KB
Line 
1##
2#
3# @file
4#
5# @brief Configure script of LibBSP for the Altera Cyclone-V platform.
6#
7
8AC_PREREQ([2.69])
9AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
10AC_CONFIG_SRCDIR([make/custom/altcycv_devkit.cfg])
11RTEMS_TOP(../../../../../..)
12RTEMS_SOURCE_TOP
13RTEMS_BUILD_TOP
14RTEMS_BSP_LINKCMDS
15
16RTEMS_CANONICAL_TARGET_CPU
17AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
18RTEMS_BSP_CONFIGURE
19
20RTEMS_PROG_CC_FOR_TARGET
21RTEMS_CANONICALIZE_TOOLS
22RTEMS_PROG_CCAS
23
24RTEMS_CHECK_NETWORKING
25AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
26
27RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
28RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
29
30RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1])
31RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache])
32
33RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1])
34RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache])
35
36RTEMS_BSPOPTS_SET([BSP_START_COPY_FDT_FROM_U_BOOT],[*],[1])
37RTEMS_BSPOPTS_HELP([BSP_START_COPY_FDT_FROM_U_BOOT],[copy the U-Boot provided FDT to an internal storage])
38
39RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_SIZE_MAX],[*],[262144])
40RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_SIZE_MAX],[maximum size of the FDT blob in bytes])
41
42RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_READ_ONLY],[*],[1])
43RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_READ_ONLY],[place the FDT blob into the read-only data area])
44
45RTEMS_BSPOPTS_SET([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[*],[1])
46RTEMS_BSPOPTS_HELP([BSP_FDT_BLOB_COPY_TO_READ_ONLY_LOAD_AREA],[copy the FDT blob into the read-only load area via bsp_fdt_copy()])
47
48RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U])
49RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
50RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
51
52RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[1])
53RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
54[This sets a mode where the time runs as fast as possible when a clock ISR
55occurs while the IDLE thread is executing.  This can significantly reduce
56simulation times.])
57
58RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[0])
59RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
60
61RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_CONSOLE],[*],[0])
62RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_CONSOLE],[configuration for console (UART 0)])
63
64RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_UART_1],[*],[0])
65RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1])
66
67RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U])
68RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs])
69
70RTEMS_BSPOPTS_SET([BSP_USE_UART_INTERRUPTS],[*],[1])
71RTEMS_BSPOPTS_HELP([BSP_USE_UART_INTERRUPTS],[enable usage of interrupts for the UART modules])
72
73RTEMS_BSPOPTS_SET([CYCLONE_V_NO_I2C],[*],[1])
74RTEMS_BSPOPTS_HELP([CYCLONE_V_NO_I2C],
75[Number of configured I2C buses. Note that each bus has to be configured in an
76apropriate i2cdrv_config array.])
77
78RTEMS_BSPOPTS_SET([CYCLONE_V_I2C0_SPEED],[*],[100000])
79RTEMS_BSPOPTS_HELP([CYCLONE_V_I2C0_SPEED],[speed for I2C0 in HZ])
80
81RTEMS_CHECK_SMP
82AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
83
84RTEMS_BSP_CLEANUP_OPTIONS
85
86AC_CONFIG_FILES([Makefile])
87AC_OUTPUT
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