source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs @ 64f7724

4.115
Last change on this file since 64f7724 was f73cfe99, checked in by Ralf Kirchner <ralf.kirchner@…>, on Jul 31, 2013 at 7:45:59 AM

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
  • Property mode set to 100644
File size: 318 bytes
Line 
1%rename endfile old_endfile
2%rename startfile old_startfile
3%rename link old_link
4
5*startfile:
6%{!qrtems: %(old_startfile)} \
7%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
8
9*link:
10%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
11
12*endfile:
13%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s }
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