4.115
Last change
on this file since 19260fb was
f73cfe99,
checked in by Ralf Kirchner <ralf.kirchner@…>, on 07/31/13 at 07:45:59
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bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
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-
Property mode set to
100644
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File size:
318 bytes
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Rev | Line | |
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[f73cfe99] | 1 | %rename endfile old_endfile |
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| 2 | %rename startfile old_startfile |
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| 3 | %rename link old_link |
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| 4 | |
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| 5 | *startfile: |
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| 6 | %{!qrtems: %(old_startfile)} \ |
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| 7 | %{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} |
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| 8 | |
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| 9 | *link: |
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| 10 | %{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} |
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| 11 | |
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| 12 | *endfile: |
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| 13 | %{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } |
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