source: rtems/c/src/lib/libbsp/arm/altera-cyclone-v/README @ 19260fb

4.115
Last change on this file since 19260fb was f73cfe99, checked in by Ralf Kirchner <ralf.kirchner@…>, on Jul 31, 2013 at 7:45:59 AM

bsp/altera-cyclone-v: New BSP

Implemented so far:

  • nocache heap for uncached RAM
  • basic timer
  • level 1 cache handling for arm cache controller in arm-cache-l1.h
  • level 2 L2C-310 cache controller
  • MMU
  • DWMAC 1000 ethernet controller
  • basic errata handling
  • smp startup for second core
  • Property mode set to 100644
File size: 91 bytes
Line 
1Evaluation board for this BSP:
2- Cyclone V SoC FPGA Development Kit
3- DK-DEV-5CSXC6N/ES-0L
Note: See TracBrowser for help on using the repository browser.